Measurement Computing PCI-QUAD-AC5 User Manual page 18

PCI-QUAD-AC5 User's Guide
The PCI-QUAD-AC5 board has open locations where you can install a 2.2 K ohm, eight-resistor single
inline package (SIP) resistor network for each port. Each of the four port locations is identified by the bit
range — the First Port connector (P1) is labeled
Bits 25 to 48, the Third Port connector (P3) is labeled
is labeled
Bits 73 to 96
adjacent to each port. Refer to Figure 4-4.
Second Port First Port
SIP locations
A, B, C (3 per port)
When installed, the SIP establishes either a high or low logic level at each of the eight
I/O lines on the port. At each board location, A, B, and C, there are 10 holes in a line. The hole on one
end is marked "HI" and is connected to +5V. The other end is marked "LO" and is connected to GND.
The eight holes in the middle connect to the eight lines of the port, A, B or C.
To pull-up lines, orient the SIP with the common pin (dot) toward the HI end; to pull-down, install the
resistor with the common pin in the LO end.
Figure 4-5 shows a schematic of an SIP installed in both the pull-up and pull-down positions.
+5 VDC
HI
n7
n6
n5
Digital
n4
I/O Port
n3
n2
n = A, B, or C
n1
n0
LO
(GND)
2.2 K SIP installed for pull-up
We recommend using 2.2KΩ SIPs (MCC part number SP-K2.29C). Use a different value only if
necessary.
. Pull-up/pull-down SIP locations (3 per port) are labeled
Figure 4-4. PCI-QUAD-AC5 layout and SIP locations
Dot indicates the
2.2 K SIP
common line
COM
Figure 4-5. Pull-up and pull-down resistor SIP schematic
, the Second Port connector (P2) is labeled
Bits 1 to 24
, and the Fourth Port connector (P4)
Bits 49 to 72
Fourth Port Third Port
+5 VDC
HI
n7
n6
n5
Digital
n4
I/O Port
n3
n2
n = A, B, or C
n1
n0
LO
(GND)
2.2 K SIP installed for pull-down
4-2
Functional Details
, and , and are
A B C
2.2 K SIP
COM
Dot indicates the
common line