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Appendix B: Programmer Guide
Table B-24: Global Interrupt Enable Register
Table B-25: Interrupt Status Register
84
0x021C
3
3
2
2
2
2
2
2
2
1
0
9
8
7
6
5
4
3
Name
Reserved
31:1
GIER
0x0220
3
3
2
2
2
2
2
2
2
1
0
9
8
7
6
5
4
3
Name
Reserved
31:6
intr_coef_mem_rdbk
_rdy
intr_reg_update_
done
intr_coef_wr_error
intr_output_error
intr_input_error
intr_coef_fifo_rdy
intr_output_frame_
done
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Software_Reset
2
2
2
1
1
1
1
1
1
2
1
0
9
8
7
6
5
4
Reserved
Bits
Reserved
0
Global Interrupt Enable Register. Active High
ISR
2
2
2
1
1
1
1
1
1
2
1
0
9
8
7
6
5
4
Reserved
Bits
Reserved
Level sensitive: Output flag indicating that the specified
6
coefficient bank is ready for reading.
Level sensitive: issued during Vertical blanking when the
5
register values have been transferred to the active
registers.
Rising edge sensitive: issued if coefficient is written into
4
coefficient FIFO when the FIFO is not ready.
Rising edge sensitive: issued if frame period completes
3
before full output frame has been delivered.
Rising edge sensitive: issued if active_video_in is
2
asserted before the scaler is ready to receive a new line.
Level sensitive: issued when the coefficient FIFO is ready
to receive a coefficient for the current set. Stays low once
1
a full set has been written into FIFO. Sent high during
Vertical blanking.
Rising edge sensitive: issued once per complete output
0
frame.
1
1
1
1
0
0
0
0
0
3
2
1
0
9
8
7
6
5
Description
1
1
1
1
0
0
0
0
0
3
2
1
0
9
8
7
6
5
Description
Video Scaler v4.0 User Guide
UG805 March 1, 2011
W
0
0
0
0
0
4
3
2
1
0
d
R/W
0
0
0
0
0
4
3
2
1
0
Int
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