Xilinx LogiCORE IP User Manual page 100

Appendix C: System Level Design
100
PARAMETER HW_VER = 6.03.a
PARAMETER C_NUM_PORTS = 6
PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y9
PARAMETER C_MEM_TYPE = DDR3
PARAMETER C_MEM_PARTNO = MT4JSF6464HY-1G1
PARAMETER C_MEM_ODT_TYPE = 1
PARAMETER C_MEM_REG_DIMM = 0
PARAMETER C_MEM_CLK_WIDTH = 1
PARAMETER C_MEM_CE_WIDTH = 1
PARAMETER C_MEM_CS_N_WIDTH = 1
PARAMETER C_MEM_DATA_WIDTH = 32
PARAMETER C_MEM_NDQS_COL0 = 3
PARAMETER C_MEM_NDQS_COL1 = 1
PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000000020100
PARAMETER C_MEM_DQS_LOC_COL1 = 0x000000000000000000000000000000000003
PARAMETER C_IODELAY_GRP = DDR3_SDRAM
PARAMETER C_MPMC_CLK0_PERIOD_PS = 5000
PARAMETER C_ARB0_ALGO = CUSTOM
PARAMETER C_ARB0_NUM_SLOTS = 2
PARAMETER C_ARB0_SLOT0 = 425310
PARAMETER C_ARB0_SLOT1 = 423510
# PIM0 (XCL)
PARAMETER C_PIM0_BASETYPE = 1
PARAMETER C_XCL0_B_IN_USE = 1
# PIM1 (Video Input)
PARAMETER C_PIM1_BASETYPE = 6
PARAMETER C_PIM1_DATA_WIDTH = 64
PARAMETER C_PI1_RD_FIFO_TYPE = DISABLED
PARAMETER C_PI1_WR_FIFO_TYPE = SRL
PARAMETER C_VFBC1_RDWD_DATA_WIDTH = 16
PARAMETER C_VFBC1_RDWD_FIFO_DEPTH = 2048
PARAMETER C_VFBC1_RD_AEMPTY_WD_AFULL_COUNT = 20
# PIM2 (Scaler IO)
PARAMETER C_PIM2_DATA_WIDTH = 64
PARAMETER C_PIM2_BASETYPE = 6
PARAMETER C_VFBC2_RDWD_DATA_WIDTH = 16
PARAMETER C_VFBC2_RDWD_FIFO_DEPTH = 2048
PARAMETER C_PI2_WR_FIFO_TYPE = SRL
PARAMETER C_PI2_RD_FIFO_TYPE = SRL
PARAMETER C_VFBC2_RD_AEMPTY_WD_AFULL_COUNT = 20
# PIM3 (OSD1 - Scaled Video Output)
PARAMETER C_PIM3_BASETYPE = 6
PARAMETER C_PIM3_DATA_WIDTH = 64
PARAMETER C_PI3_RD_FIFO_TYPE = SRL
PARAMETER C_PI3_WR_FIFO_TYPE = DISABLED
PARAMETER C_VFBC3_RDWD_DATA_WIDTH = 16
PARAMETER C_VFBC3_RDWD_FIFO_DEPTH = 2048
PARAMETER C_VFBC3_RD_AEMPTY_WD_AFULL_COUNT = 20
# DDR3 Parameters
PARAMETER C_MPMC_BASEADDR = 0x10000000
PARAMETER C_MPMC_HIGHADDR = 0x1FFFFFFF
BUS_INTERFACE XCL0 = microblaze_0_IXCL
BUS_INTERFACE XCL0_B = microblaze_0_DXCL
BUS_INTERFACE VFBC1 = vdma_0_XIL_VFBC
BUS_INTERFACE VFBC2 = vdma_1_XIL_VFBC
BUS_INTERFACE VFBC3 = vdma_2_XIL_VFBC
PORT MPMC_Clk0 = clk_200_0000MHzMMCM0
PORT MPMC_Clk_200MHz = clk_200_0000MHzMMCM0
PORT MPMC_Rst = sys_periph_reset
PORT MPMC_Clk_Mem = clk_400_0000MHzMMCM0
PORT MPMC_Clk_Rd_Base = clk_400_0000MHzMMCM0_nobuf_varphase
PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN
PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC
PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE
PORT DDR3_Clk = fpga_0_DDR3_SDRAM_DDR3_Clk_pin
PORT DDR3_Clk_n = fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin
PORT DDR3_CE = fpga_0_DDR3_SDRAM_DDR3_CE_pin
PORT DDR3_CS_n = fpga_0_DDR3_SDRAM_DDR3_CS_n_pin
PORT DDR3_ODT = fpga_0_DDR3_SDRAM_DDR3_ODT_pin
PORT DDR3_RAS_n = fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin
PORT DDR3_CAS_n = fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin
PORT DDR3_WE_n = fpga_0_DDR3_SDRAM_DDR3_WE_n_pin
www.xilinx.com Video Scaler v4.0 User Guide
UG805 March 1, 2011