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b. Queue Algorithm Qualifier
This parameter controls the execution order algorithm of a command issued together with
a SIMPLE QUEUE TAG message.
When "0" is specified in this parameter, the IDD executes commands queued from each
INIT in the order in which they were received. However, the command execution order
for the READ, READ EXTENDED and PRE-FETCH commands may be changed.
When "1" is specified in this parameter, the IDD executes queued commands by the
method selected by the IDD. At this time, the INIT must verify the correctness of the data
through appropriate commands and QUEUE TAG messages.
c. QErr (queue error management)
This bit controls processing of commands queued after a sense hold state is canceled when
the IDD is in the sense hold state.
When "0" is specified in this bit, the IDD, when it has been in any one of various sense
hold states, then that sense hold state is cleared, continues executing the commands which
are queued by normal methods.
When "1" is specified in this bit, the IDD, when it has been in any one of various sense
hold states, then that sense hold state is cleared, clears the commands which are queued.
At this time, the IDD generates a UNIT ATTENTION condition (Command cleared by
another initiator =2F-00]) for each of the INITs that issued the commands which were
cleared.
d. DQue (disable queuing)
This bit specifies whether the IDD will execute processing of tagged commands or not.
When "0" is specified in this bit, the IDD permits tagged queuing processing.
When "1" is specified in this bit, the IDD prohibits tagged queuing processing. The IDD
clears queued commands and generates a UNIT ATTENTION condition (Command
cleared by another initiator =2F-00]) for each of the INITs that issued the commands
which were cleared. After that, the when a QUEUE TAG message is received, it is
rejected with a MESSAGE REJECT message and executed as an untagged command.
e. EECA (enable extended contingent alliance)
This bit specifies whether or not the ECA state is permitted.
"1" : The IDD supports the ECA state.
"0" : The IDD does not support the ECA state.
This bit cannot be changed. The IDD disregards the specification of this bit and operates
according to the "Default" value. (= "0").
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C141-E039-01EN
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