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QQ
3 7 63 1515 0
Pin No.
Pin Name
66
VDD
67
CAEN
68
CCS
69
CWE
70
COE
71
CBUSY
72
VDD
73
GND
74 ~ 79
CODE7 ~ CODE2
80
GND
81, 82
CODE1, CODE0
83
VDD
84 ~ 91
DATA7 ~ DATA0
92
DINT
93
DREQ
94
VDD
95
DACK
96
CS
97
WR
TE
L 13942296513
98
RD
99
VDD
100
INT
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I/O
—
Power supply (+5 V)
O
Numbers of access synchronous output of device connected to CODE bus. "L": Synchronized (Notused)
O
Control output of device connected to CODE bus (Not used)
O
Compression data write signal output to device connected to CODE bus (Not used)
O
Compression data read signal output to device connected to CODE bus (Not used)
I
BUSY signal input from device connected to CODE bus (Not used)
—
Power supply (+5 V)
—
Ground
High speed access to compression data during master mode. During compression: Output.
I/O
During expansion: Input
—
Ground
High speed access to compression data during master mode. During compression: Output.
I/O
During expansion: Input
—
Power supply (+5 V)
I/O
Host data bus input/output
O
Interrupt signal output
O
DMA transfer request signal output to host. "L": Request
—
Power supply (+5 V)
I
DMA transfer acknowledge input from host. "L": Acknowledge
I
Chip select input from host. "L": Active
I
Host data bus write signal input
I
Host data bus read signal input
—
Power supply (+5 V)
O
Interrupt request output to host. "L": Acknowledge
x
ao
y
i
— 138 —
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8
Description
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