Sony DPA-300 Service Manual page 58

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• IC104 FRONT END (SAA7110AWP) / VIDEO-IN BOARD
Pin No. Pin Name I/O
1 SHIFTTP I
2 ACTP I
3 RTCO O
4 IICSA I
5 SDA I/O
6 SCL I
7 ~ 9 RSRV1 ~ RSRV3 —
10 VSSA4 —
11 AI42 I
12 VDDA4 —
13 AI41 I
14 VSSA3 —
15 AI32 I
16 VDDA3 —
17 AI31 I
18 AVSS2 —
19 AI22 I
20 AVDD2 —
21 AI21 I
TE
L 13942296513
22 VSSS —
23 AOUT O
24 VDDA0 —
25 VSSA0 —
26 LFCO O
27 VDD —
28 VSS —
29 LLC I/O
30 LLC2 O
31 CREF I/O
32 RESO I/O
33 CGCE I
34 VDD —
35 VSS —
36 HCL I/O
37 HSIND I/O
38 HSYNC O
39 PLIN O
40 ODD/EVEN O
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Test pin. (Fixed to "L")
Test pin. (Fixed to "L")
Real time control output (Not used)
IIC bus slave address selection signal input (Not used)
"L": Slave address = 9CH write, 9DH read
"H": Slave address = 9DH write, 9FH read
IIC bus serial data input/output
IIC bus serial clock input
Not used
Analog Ground-4
Analog input (Not used)
Analog power supply-4 (+5 V)
Y (luminance) signal analog input
Analog Ground-3
C (chroma) signal analog input
Analog power supply-3 (+5 V)
Y (luminance) signal analog input
Analog Ground-2
C (chroma) signal analog input
Analog power supply-2 (+5 V)
Analog input (Not used)
Sub-state Ground
Analog test output (Not used)
Power supply for internal clock circuit (+ 5 V)
Ground for internal clock circuit
External clock circuit control signal output (Not used)
Power supply (+5 V)
Ground
Line lock clock input/output (32 MHz). Pin-33 CGCE is "H": Output, "L": Input
1/2 signal output of line lock clock (16 MHz). Pin-33 CGCE is "H" output, "L": High impedance
Reference clock input/output. Pin-33 CGCE is "H": Output, "L": Input (Not used)
Reset input/output. Pin-33 CGCE is "H": Output, "L": Input (Not used)
Internal clock circuit enable input. (Not used)
Power supply (+5 V)
Ground
Horizontal clamp pulse input/output (Not used)
Horizontal sync display signal input/output (Not used)
Horizontal sync signal output
Not used
ODD/EVEN identification signal output
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Description
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