Sony DPA-300 Service Manual page 80

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Pin No. Pin Name I/O
71 X1 I
72 GND —
73 UCAS O (3)
74 LCAS O (3)
75 GND —
76 VDD —
77 RAS O (3)
78 UMWR O (3)
79 LMWR/WE O (3)
80 MRD O (3)
81 READY I
82 CS0/REFRQ O (3)
83 ~ 85 CS1 ~ CS3 O (3)
86 ~ 90 A12 ~ A16 O (3)
91 GND —
92 VDD —
93 ~ 97 A17 ~ A21 O (3)
98 A22 O (3)
99 A23 O (3)
100 VDD —
* (3) of I/O is 3-state output.
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Clock input (4 MHz)
Ground
Column address strobe signal output to higher data of DRAM
Column address strobe signal output to lower data of DRAM
Ground
Power supply (+5 V)
Row address strobe signal output to DRAM
Write strobe signal output to higher data of memory
Write strobe signal output to lower data of memory
Read strobe signal output to memory
Bus cycle end ready signal input (Not used)
Chip select signal, or refresh request signal output to DRAM (Not used)
Chip select signal output
Address bus output
Ground
Power supply (+5 V)
Address bus output
Address bus output (Not used)
Address bus output
Power supply (+5 V)
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Description
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