Sony DPA-300 Service Manual page 60

QQ
3 7 63 1515 0
• IC105 JPEG ENCODER/DECODER (MD2201A) / VIDEO-IN BOARD
Pin No. Pin Name I/O
1 RSTI I
2 TEST —
3 WR I
4 RD I
5 CS I
6, 7 HA0, HA1 I
8 DACK I
9 GND —
10 DREQ O
11 INT O
12 VDD —
13 ~ 20 D0 ~ D7 I/O
21 ~ 24 Y7 ~ Y4 I/O
25 VSS —
26 VDD —
27 ~ 30 Y3 ~ Y0 I/O
31 ~ 33 C7 ~ C5 I/O
34 VSS —
35 ~ 39 C4 ~ C0 I/O
TE
L 13942296513
40 SWE I
41 DOE I
42 HBLK I
43 VBLK I
44 ODD/EVEN I
45 VDD —
46 VSS —
47 HOUT O
48 DSPLY O
49 RFSH O
50 OE2 O
51 WE2 O
52 OE1 O
www
53 WE1 O
54 RAS O
55, 56 AD7, AD6 I/O
.
57 VDD —
58 VSS —
http://www.xiaoyu163.com
Reset input
Test terminal. (Fixed to "L")
Data bus write signal input
Data bus read signal input
Data bus chip select signal input
I/O address input
DMA transfer acknowledge signal input. (Compressed data and picture data only are valid.)
Ground
DMA transfer request signal output. (Compressed data and picture data only are valid.)
End signal output of the respective mode processing. "L": Mode ended. "H": Mode is continued or mode has
not started yet
Power supply (+5 V)
Data bus input/output. (Compressed data, picture data, command, status)
Y-data bus during synchronous pixel input/output
Ground
Power supply (+5 V)
Y-data bus during synchronous pixel input/output
Cb/Cr-data bus during synchronous pixel input/output. (Cb and Cr are mutually interleaved when input and
output.)
Ground
Cb/Cr-data bus during synchronous pixel input/output. (Cb and Cr are mutually interleaved when input and
output.)
DRAM selection input
DRAM control
L
WE1 Active at CAS address
OE1 0 to 511
WE2 Active at CAS address
512 to 1023
OE2
DRAM control setting put. "L": Normal access, "H": Hi-Z
Horizontal sync data effective period input during sync signal input/output.
(Refresh operation during blanking period Data access during real display mode.)
Vertical sync data effective period input during sync signal input/output.
Odd/even field identification signal input during sync signal input/output.
"H": First field, "L": Second field
Power supply (+5 V)
Ground
HBLK is delayed for the time equivalent to internal processing time, and is output. (Not used)
Status output indicating that Y/C data bus is output status when this pin is "H"
DRAM status output. "L": During refreshing, "H": Normal operation
Read enable signal 2 output
Write enable signal 2 output
Read enable signal 1 output
Write enable signal 1 output
x ao u163
y
Row address selection signal output
Y data bus input/output with DRAM
i
Power supply (+5 V)
Ground
— 114 —
http://www.xiaoyu163.com
2 9
8
Description
Q Q
3 6 7 1 3 1 5
SWE
R
Active at CAS address
0 to 1023
Active at CAS address
1024 to 2047
co
.
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9