Sony DPA-300 Service Manual page 68

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• IC1005
PICTURE MEMORY CONTROLLER (CXD8648R-AV) / PICTURE BOARD (1/3)
Pin No. Pin Name I/O
1 XWR I
2 XDRQ O
3 XDACK I
4 GND —
5 WEND O
6 FDO O
7, 8 A2, A1 I
9 VCC —
10 ~ 25 D15 ~ D0 I/O
26 GND —
27 TP2 —
28 VCC —
29 ~ 37 VA0 ~ VA8 O
38 DSF O
39 GND —
40 CAS O
41 VCC —
42 RAS2 O
43 RAS1 O
44 WEH O
45 WEL O
TE
L 13942296513
46 TP3 —
47 ~ 54 VD15 ~ VD8 I/O
55 GND —
56 ~ 63 VD7 ~ VD0 I/O
64 VCC —
65 ~ 67 TP4 ~ TP6 —
68 SE2 O
69 SE1 O
70 OE2 O
71 OE1 O
72 TP7 —
73 SDAT I
74 GND —
75 SCLK O
76 VCC —
77 ADAK O
78 ADRQ I
79 TEST I
80 GND —
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Host data bus write signal input. "L": Active
Low pulse is output during DMA transfer request
DMA acknowledge signal input. "L": Active
Ground
JPEG stream window end signal output. "L": End
Register set timing frame pulse output during the picture-input lock mode. "L": Active (Not used)
Address input from host CPU
Power supply (+5 V)
Data bus input/output with host CPU
Ground
Not used
Power supply (+5 V)
Address output to VRAM
Special function enable signal output to VRAM
Ground
Column address strobe signal output to VRAM
Power supply (+5 V)
Row address strobe signal output to VRAM (Not used)
Row address strobe signal output to VRAM
Upper bytes data write enable signal output to VRAM
Lower bytes data write enable signal output to VRAM
Not used
Data bus input/output with VRAM
Ground
Data bus input/output with VRAM
Power supply (+5 V)
Not used
Serial data enable output to VRAM (Not used)
Serial data enable output to VRAM
Data transfer/output enable output to VRAM (Not used)
Data transfer/output enable output to VRAM
Not used
Serial clock input from digital NTSC encoder
Ground
Serial clock output to digital NTSC encoder
Power supply (+5 V)
Address acknowledge output to digital NTSC encoder. "L": Active
Address transfer request input from digital NTSC encoder. "H": Active
Test pin (Fixed "L")
Ground
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Description
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