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98640A Analog Input Interface
15
14 13
12
11 10
9
8
7
6
5
4
3
2
1
o
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
IBlwlolslnlDIDIDIDIDIDIDIDlnlDIDI
+---+- .. -+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
MSB
LSB
where:
B
=
busy. If this bit is set to 1, the card is busy; the remaining bits in the data word are invalid,and
the address provided in the read request is not accepted by the card. If this bit is set to 0, the data
word is valid and the address is latched by the address latch on the card. This bit is the inverse of bit
6 of the status register.
W
=
wait. If this bit is set to 1, the card is in the wait state and the analog read will not
be
properly
paced (according to the value programmed into the pace timing register). If this bit is set to 0, the
card is not in the wait state and the read will be properly paced.
o
=
common mode overrange. This bit is negative true. If this bit is set to 0, a common mode over-
range occurred during the reading; the value in the remainder of the data word is invalid. If this bit is
set to 1, no common mode overrange occurred during the reading.
S
=
sign. If this bit is set to 0, the voltage value in the D bits is positive. If this bit is set to I, the volt-
age value is negative.
D
=
data. These twelve bits give a binary value for the magnItude of the voltage. Bit 11 is the most
significant bit (MSB); bit 0 is the least significant bit (LSB). This is the raw value provided by the
ADC on the card; it has not been adjusted for gain.
The meanings of these bits are covered in greater detail in the remainder of this section.
Pace Timing Register
The pace timing register controls the pace interval between readings. This is a 16-bit register located
at register address 4 on the A -to-D card. To calculate the register value that corresponds to a given
pace period, use:
FFF6(hex) - round((period - 0.000018) / 0.0000006)
where period is the desired pace interval in seconds, and where
round
is a function that rounds a value
to the nearest integer. To place that value into the pace timing register, simply write the value to
register address 4. The A-to-D card allows pace periods from 18 microseconds to 39.3390 mil-
liseconds, with a resolution of 600 nanoseconds.
10 Register
The ID register is an 8-bit register hard-wired with a value of 18 (the
10
number of the A-to-D
card). It is located at register address 1 on the A-to-D card. Reading from this register returns a
value of 18. Writing to this register causes a soft reset of the A -to-O card; this sets the BUSY bit to 0
and resets the PROM counter to O.
3-4
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