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98640A Analog Input Interface
BUSY- sets ADDRESSGRAB low (and ADDRESSGRAB- high) on the next falling edge of the clock.
ADDRESSGRAB- enables U85, and this situation is maintained until LACH goes high, which sets
BUSY low. Thus, BUSY is high continuously from clock cycle 0 of the Conversion state machine to
clock cycle 4.5; this allows the address to be clocked into the card and data to be moved to the output
buffers without interruption.
The BUSY signal is available to the backplane as bit 15 of the data register; BUSY-is available as bit
6 of the status register. Whenever BUSY is low, the card can accept a new address from the
backplane. The WAIT signal is available as bit 14 of the data register; if WAIT is high, it indicates
that the interval before the next analog reading will be longer than the interval programmed into the
pacing timer. (That's because the card is stopped and waiting for the next address.) Note that the
BUSY and \VAIT bits are not clocked to the output buffers (in contrast to the overrange, sign, and
data bits); the current states of BUSY and WAIT are always available, regardless of what part of the
cycle the state machine is in.
The Internal Pacing Timer
The internal pacing timer comprises four 4-bit counters, U36, U26, U47, and U48. These are set up in
series such that they will count from a programmed start value up to FFFF(hex). The counters use the
system clock as the time base, with each count taking 600 nanoseconds. When the BUC/D- signal
goes low, it loads the pacing timer with the values contained in flip-flops U37 and U49. When
BUC/D- goes high again, the pacing timer is enabled to count. It starts counting on the next positive
transition of the system clock, and counts continuously until the BUC/D- goes low again to reload the
timer.
The carry bit of the most significant counter (U 4
7)
drives the ENDCT signal. This signal is used to
restart the Conversion state machine counter after the programmed pace interval has elapsed.
ENDCT remains high while the pacing timer counts up toward FFFF. When the timer reaches FFFF,
ENDCT is driven low.
A typical conversion cycle starts off with BUSY set high by an analog read. Shortly afterward
BUSAMP goes high, and BUC/D- goes low on the following clock cycle. The BUC/D- transition
presets the pacing timer with the values from flip-flops U37 and U49. On the next clock cycle
BULACH goes high, setting BUSY low. Two cycles later, BUC/D- goes high, allowing the timer to
count on positive clock cycles. Later in the conversion cycle PACEN will go high; since ENDCT stays
high while the timer is counting up toward FFFF, PACEN and ENDCT will combine to cause U92 to
stop the counter. (Yes, you must keep PACDA high, too. That's under your control. You keep.
PACDA high by keeping the internal pace disable input (IPACDA, terminal 30) low. IPACDA must
alwa~
be low unless you are doing external pacing, as described below.) The counter will remain stop-
ped until the timer reaches FFFF; that sets ENDCT low and releases the counter to continue the con-
version cycle"
The value that you write to the pace timing register to obtain a given pace period is:
value
=
FFF6(hex) -
round«period - 0.000018) / 0.0000006)
where the period is given in seconds and the
round
function rounds to the nearest integer. This for-
mula compensates for the difference between when the timer starts counting (clock cycle 7) and when
PACEN goes high (clock cycle 15). Remember that ENDCT goes low when the timer reaches FFFF,
not when it rolls over to O.
Note that you can squeeze in a few extra microseconds beyond the maximum pace period indicated by
this formula if you specify a value between FFF7 and FFFF. For values in that range, the timer will
3-19
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