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98640A Analog Input Interface
c
ca bling, 2 - 8
a ttaching wires,
2 - 8
ground -loops, 2 -1 0
shielded, 2 - 8
strain relief,
2-8
wire,
2-8
wire bundles,
2 -1 0
calibration
(reasons for), 4 - 3
detailed, 4 - 4
quick, 4-5
polarity effects,
4-7
card assembly number,
1-2
channels (see also cabling), 1 - 1
cleaning contacts,
2-1
clock cycle, 3 - 1 4
clock rate, 1- 3
common mode over range, 3 -10
bit, 3-13
detection, 3 - 1 3
signal (OVD-), see signals
controllines\ voltage source for, 4-12
con version cycle, 3 - 1 7, 3 - 1 8
Conversion state machine, 3-1, 3-13
control, 3-17
clock cycles 0 to 4.5, 3 -1 9
reset, 3-22
restart counter, 3-19
stuck at cycle 16, 3-20
converting to a voltage, 4- 5
counter, release, 3-17
cover plate, 1 -1, 2 - 5, 2-7
CPC, 1- 2, 2 - 1 2
CPC, 2-12
custom resistor network, 3-7
D
data buffer, 3-18
data register, 3- 3
data word
availability (BUSY and Wait), 3-19
Busy bit, 3-19
magnitude,
4-3
Obit, 3-13
overranges,
4-7
returned value, 4- 2
ra w reading, 4- 3
sign bit, 4- 3
WAIT bit, 3-19
Diff eren tial-to -single -ended -con verter, 3 - 1 0
INDEX-2
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