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98640A Analog Input Interface
Assume that we are starting at clock cycle 0 with BUSY low, waiting for an analog read. As described
above, \\' AIT is high at clock cycle O. With WAIT high and BUSY low (BUSY-high), the counter is
stopped. When the analog read occurs, BUSY is set high, the counter is released, and the state machine
moves into the conversion cycle. As the card leaves the wait state, BURD- is pulled low. On the next
clock cycle, BUSAMP goes high. This accomplishes three things:
1) It
puts the sample and hold circuit in the sample state.
2)
It
latches the overrange bit, the polarity bit, and the 4 most significant data bits (from the ADC)
into data buffer U7 8.
3)
It
clocks the address from address buffer U50 into buffer U70.
On the next cycle BUC/D- goes low, enabling the ADC to release the 8 least significant data bits and
loading the value from the pace timing register into the pace timer. LACH and BULACH go high on
the following cycle; this sets BUSY low again and clocks those 8 data bits into data buffer U77.
In the next few cycles, BURD- goes high, causing the data lines at pins 9, 8, and 7 of the ADC to go
low; BUC/D- goes high, enabling the pacing timer to start counting; and BUWR - goes low. On this
last transition, the mode of the ADC is programmed. All of this activity takes us through clock cycle
7.
At clock cycle 15 the PACEN signal is raised. This allows the counter to be stopped by either the ex-
ternal pace input or the internal pacing timer. This stop condition will persist as long as the external
pacing input is actuated, or until the internal pacing timer reaches full value. At that point the con-
version cycle will continue. On the next cycle, BUC/D- will go low, followed by BUWR-, BULACH,
and BUSAMP one cycle later. As a result, conversion begins on the voltage held by the sample and
hold circuit; in addition, the polarity and overrange signals (POLAR - and OVD-) are clocked into the
flip-flops in U96.
After allowing time for the conversion to complete, the START signal goes high. This resets the
counter to 0, causing the PROM to start the conversion cycle over again.
The BUSY Cycle
As you might infer from the discussion of the conversion cycle, the BUSY signal plays a significant
part in controlling the conversion.
It
is the signal that starts the conversion cycle, or causes it to stop
in the wait state. The BUSY signal is controlled by its own state machine, which consists of two
J-K
flip-flops (U 8 5) and a gaggle of gates (U 84). Figure 3-7 shows a timing diagram of the BUSY cycle.
An analog read puts a valid address on the address bus, causing ININT to go high (after the card
decodes its address via U39). The output of U46 is set on the next rising edge of the system clock, and
this gates IA6 (the analog read "flag") through U85A. TACH- subsequently goes low, causing
DT ACK - to acknowledge the command from the backplane.
Assume that at this time BUSY- is high and the card is in the wait state; this combination (BUSY- and
WAIT both high) will cause U92 to stop the counter. BUSY-will therefore gate the high output of
U85A through U84A, causing ADDRESSGRAB to go high on the next falling edge of the system
clock. When ADDRESSGRAB goes high, it clocks the address from the backplane into address buffer
U50.
When the address is removed from the backplane and IA6 goes low, ADDRESSGRAB gates a high
level through U84D, setting BUSY high and BUSY- low. This releases the counter, and the conversion
cycle continues on the next rising edge of the system clock.
3-18
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