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98640A Analog Input Interface
POWER AND TIMING
Card Power Supply
The power that drives the A-to-D card is supplied by the host computer. The +5 volt, +12 volt, and
-12 volt supplies come off the backplane and pass through appropriate inductors and capacitors to
help stabillize the voltages. The +5 volt supply is also routed to terminal 28 on the wire termination
assembly. (This voltage is supplied for your convenience in external pacing applications; it is not in-
tended to be a general purpose power supply.)
System Clock
The system clock signal (SYCLK) for the A-to-D card is generated by the clock chip, VI 00. Since the
clock generates TTL levels, no interface circuit is needed. The clock frequency is 1.667 MHz, or one
clock cycle every 600 nanoseonds, hence the minimum increment available for internal pacing. Note
that the clock on the card is not synchronized with the host computer's clock.
REGISTERS
To make an analog read from the A -to-D card, you must specify a register address in your read
request. The register address encodes the channel you want to read, and the gain at which you want to
read it, in the following way:
Address for
Address for
Address for
Address for
ChannE!l
gain of
1
gain of
8
gain of
64
gain of
512
0
64
80
96
112
1
66
82
98
114
2
68
84
100
116
3
70
86
102
118
4
72
88
104
120
5
74
90
106
122
6
76
92
108
124
7
78
94
110
126
For example, if you wanted to read from channel 3 at a gain of 8, you would specify a register address
of 86 in your read request.
The value returned by an analog read is the voltage for the channel and gain specified tW.!Lana)og
readu.revi~)uili.
(Refer to the paragraphs on the "Analog Pipeline" at the end of this section for a
fuller explanation of this phenomenon.) The format for the returned value is:
3-3
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