Table of Contents
Advertisement
28
o
rvvv-
DO
01
n::>
03
04
05
06
07
DB-
09
010
011
012
013
014
015
BLOS
BUDS
RESET
BR!W
~
A
2
Analog Input Interface
21
26
25
24
+5
ENT~
ENP 7
3
CLR 1
4
C 15
5
t+k-
NC
6
U36
~NC
2
~NC
~
LD
ri1--NC
8
16
77
18
2
IDa
IDO
3
2
78
17
3
101 ,
NTERNAL' ID1
4
5
8
16
79
16
4
ID2,
DATA
'/ ID2
7
U37
6
+5
80
15
U38
5
ID3,
V
103
8
9
U26
~
81
14
6
ID4,
BUS
'I'
ID4
13
12
3
CLR
82
13
7
105 _,
V
ID5
14
15
4
ENT
7
83
12
8
106 ,
'I'
106
~7
16
5
ENP
84
11
9
ID7 _,
V 101
18
19
6
C 15
f#L-
,
'I'
.-Jf
2
~NC
EN
I>
+5
r-L-
+5
SYCLK[]D-
~
~~Ir
EN
LO
13 ..
~
10~
~NC
C29
T
110 120
BUC!D
IT:D--
t-=--'--
NC
110 120
W
110 120
\V
+5
87
11
2
ID15
ID15
3
2
3
CLR~
B8
12
3
ID1L!.'
I'
1014
4
5
4
89
13
U29
4
ID i::r'\
'/
run
7
U49
6
5
90
14
5
ID1<,
v
ID12
B
9
6
ENT 10
91
15
6
ID 11_,
'/
ID11
13
11
;:>
2
ENP 7
92
16
7
101o_,
V
IDl0
14
15
~
LD
C
15
93
17
8
109 _,
'/
IDJi
17
16
11
94
18
Ji
108 _,
V
ID8
18
19
U48
'T2
NC
rr
NC
EN
p1JL
,
V
~
I>
~NC
~
1
EN
t-"-'-
NC
18
16
(
A15
0
lIMA
[QD--
B
16
10
3
ENT 7
43
1
~ININT
4
ENP
~3
5
U47
r4-NC
6
~NC
44
1
2
~
~NC
~11
+l5
LD
~NC
1 CLR
Cci2
j C L R l
~6
5
37
5
U97
U94 6
B4
RESET
4
+5
14
READ
12
lA6 B7
i l
U94
TIME C5
~
+5
+5
14
+5
~2
45
f
5
14
5
6
2
6
9
4
U85
~8
8
1
U95
TACH C21
10
r- _ _ _
9J
U81
10
7
A14 STSTAT
7
STATUS C5
1
1
0
13
I
U95
12
7
+5
~
n
It-JINT
\/
SYCLK
I
C311 +5
W
14 U82
91'
8
B5
7
ADORES
11
A16
- -
ANEN
3
B1
IDEN
ZJ
AOORESSGRAB
ENOCT
LACH
SGRAB
11
- - -
A13 STATEN
La
Lry-14
-
C5
W
Lno
10
~8
CLR2
+5
B2
l
21
25
24
2
U99
~
'3
NC
10
:
9
NC
22
+5
~
~3~
11
NC
21
AOORESSGRAB
AOORESSGRAB
ADDRESS GRAB
BUSY
BUSY
BUSY
BUSY
BUSY
21
o
B
A
Figure 7-4. A -to-D card schematic diagram, sheet 3 of 3.
7-9/7-10
Advertisement
Table of Contents
