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98640A Analog Input Interface
card is; second, it compares the upper 8 bits of an address with the select code to determine whether
the card is being addressed. This function is implemented with an 8-bit comparator (U39), 5 of the 7
switches on DIP switch SW 1, and 5 of the 7 resistors in resistor pack RIO.
One side of each resistor in the SIP is tied high to form a pull-up resistor. The other side of each resis-
tor is tied to a switch that can be closed to ground. This connection also provides the signal to drive
other devices.
Com para tor U 3 9 compares address lines A 16 through A 23 from the backplane with the select code
switches (pins 9, 7, 5, 3, and 12) and the hard-wired bits (pins 14, 16, and 18). If the two sets of sig-
nals match, and if backplane address strobe BAS- coming in to pin 1 is low, the comparator will drive
lIMA - (pin 19) low. This tells the card that it is addressed, and also enables the DT ACK - and IMA-
drivers to drive the backplane.
The Backplane Handshake
When the II1\1A- signal goes low, the backplane data strobes (BUOS- and BLOS-) are enabled to drive
ININT high. The logic for this operation is shown at location B27 on the schematic diagram, using
two OR gates and a NAND gate. When ININT goes high, flip-flop U 46B will drive its
Q
output high
on the next rising edge of the system clock (SYCLK). One clock cycle later, that
Q
output will drive
flip-flop U 46A high and its
Q-
output will go low. This low output is designated the TACH-signal,
and it drives the DT ACK - signal on the backplane low.
When the CPU removes the card address from the backplane, the ININT signal goes low. This clears
both flip-flops in U46 and leaves the circuit ready for another I/O operation.
Addressing
The several different operations that can be done on the A -to-O card are decoded with the circuitry
at locations B to C6, 7, and 8 on the schematic diagram. Only the first 6 address lines, A 1 through A6,
are required to address the card. Because the backplane is capable of driving only one TTL load for
each input signal, most of the lower address lines go through some sort of buffer gate before they
reach a decoder or register.
Address bit 6 is used to designate an analog read (or write).
NOTE
Analog writes are emphatically NOT recommended be-
cause, if the the busy bit is low, the address data is
retained but the data from two readings ago will have
no where to go. It will be overwritten.
If address bit 6 is high and lIMA is high, signal IA6 is set high. This signal is used to disable the 3-bit
decoder at U69, to tell the BUSY state machine that an analog read is taking place, and to enable
analog data buffers U77 and U78 to drive the internal data bus.
Address bits 4 and 5 specify the gain used in an analog read. These address bits are first clocked into
address
bufff~r
U 50, and then into buffer U70. From there they drive the analog mux that selects the
gain of the programmable gain amplifier.
3-21
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