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98640A Analog Input Interface
In the equilibrium state, there will be a difference of 0.01 volts between the -
inputs of the two op amps. As a result, there will be a current of 10 microamps
flowing in the 1 kohm resistor in the feedback string. From this, we can calcu-
la te that the voltage across each of the 255.5 kohm resistors in the string will
be 2.5 55 volts.
Thus, the output voltage from the positive op amp will be +3.01+2.555=+5.565
volts, and
the
output voltage from
the
negative
op amp
will be
+3.00-2.555=+0.445 volts. The differential output from the op amps is 5.12
volts, which is 0.01 volts multiplied by a gain of 512.
The only time that the PGA does not work properly is when an input voltage causes an op amp to try
to drive its output past
±
10 volts. At that point the output clips and you have a common mode over-
range condition.
Differential-to -Single -Ended Converter
The differential-to-single-ended converter is used to translate the differential output of the PGA to
a single-ended voltage that the Sample and Hold (S/H) circuit can handle. The gain through this con-
verter is unity
(1).
The resistors in this circuit are contained in the precision resistor network (U24),
since high precision is necessary to keep the voltages accurate. Figure 3-5 is a diagram of the con-
verter circuit.
The voltage at the positive input of the op amp (U32) is half the voltage coming from the positive op
amp of the PGA (Vin+), due to the resistive divider network in U24. Similarly, the voltage at the
negative input of op amp U32 is half way between the output voltage of U32 (Vout) and the voltage
coming from the negative op amp of the PGA (Vin-). Op amp U32 drives its output (pin 7) so that the
voltages at its negative input (pin 2) and positive input (pin 3) are equal; the resulting output voltage
equals the difference between the positive and negative voltages coming from the PGA.
Example
Consider the case where the voltages coming in from the PGA (Vin+ and Vin-)
are -3 volts and +1 volt: The voltage at the + input of the op amp is -1.5 volts.
The op amp will drive its output (V out) so that a voltage of -1. 5 volts is present
at the - input also. The output voltage thus produced will be -4 volts, and this
voltage will be sent to the sample and hold circuit.
The two 330 pf capacitors in the converter circuit act as a low pass filter, which helps to reduce high
frequency noise in the circuit.
Sample and Hold (SIH) Circuit
The S/H circuit (U 12) is used to maintain a steady voltage to the analog-to-digital converter.
Capacitor C4 is the hold capacitor for this circuit, and the BUSAMP (buffered sample) signal is the
state control signal. When BUSAMP is high, the S/H circuit is in the sample mode and the capacitor is
being charged with the voltage applied at pin 3. When BUSAMP is low, the S/H circuit is in hold
mode, maintaining the voltage that it was charged to during the sample period. The S/H output (pin
5) feeds the next portion of the circuit.
3-10
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