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98640A Analog Input Interface
Remember that the buffered control signals change state one half clock cycle after their unbuffered
coun terparts.
0.0
Start of cycle. WAIT goes high.
If BUSY - is low, the conversion cycle goes on without interruption.
If
BUSY - is high, the
conversion counter stops until it goes low again. (In essence, BUSY - high means that the
card is waiting for an analog read to take place. Once the analog read starts, it will take
from 3 to 4 clock cycles before BUSY-goes low again and the conversion counter starts
counting again. During that time the backplane reads the data, and the new address is
clocked into the address buffer. Two clock cycles later, BUSY-goes low, the conversion
counter is released, and the cycle continues.)
(Note that you can keep the cycle from stopping by making sure that the analog read takes
place in time for the card to be busy (BUSY - low) when the WAIT signal goes high. The
surest way to do this is to start your next analog read as soon as BUSY - goes high again.
You can determine when that happens by checking bit 6 of the status register, or by
repeatedly checking bit 15 of the returned analog data word.)
1. 0
WAIT goes low.
1.5
BURD- goes low. This enables the transfer of the 4 most significant bits from the ADC.
2.5
BUSAMP goes high. This has three effects:
The sample and hold circuit starts sampling.
The polarity bit, the overrange bit, and the 4 most significant data bits are clocked into
the internal data buffer and onto the
int~rnal
data bus.
The address is clocked from the address buffer into buffer U70; this drives the channel
and gain multiplexers.
3.5
BUC/D- goes low. This has two results:
It
enables transfer of the 8 least significant data bits from the ADC.
It
loads the value from the pace timing register into the timer.
4.0
LACH goes high.
4.5
As a result, BUSY - goes high.
BULACH goes high. This clocks the 8 least significant data bits into the internal data
buffer and onto the internal data bus.
5.5
BURD- goes high.
6.5
BUC/D- goes high. This enables the pace timer to start counting.
7.0
The pace timer starts counting.
It
continues counting up on every positive transition of the
clock.
3-24
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