Processors - Intel SE7500CW2 Technical Product Specification

System BIOS
can be a time consuming process. Therefore, the BIOS tests only the minimum amount of
memory (1 MB) before video is displayed and it tests the remaining memory after video is
initialized. In addition, the BIOS displays the status of extended memory test on the console if
diagnostic messages are enabled.
The SE7500CW2 server BIOS implements a 32-bit, fast, enhanced memory test. The code
supports page table extensions as defined in the Pentium
capable of accessing memory above 4 GB and skipping the memory hole. The user can select
the coverage for extended memory tests by selecting the desired memory test option in the BIOS
Setup Utility. The BIOS can test every location (extensive), one "interleave width" per KB of
memory (sparse), or one "interleave width" per MB of memory (quick), depending on user
preference.
The "interleave width" of a memory subsystem depends on the chipset configuration. For 2:1
interleave, the interleave width is 128-bits. By default, the BIOS tests one "interleave width" per
MB of memory for base as well as extended memory. This default was selected to reduce the
time spent in POST. The extended memory test can be aborted by pressing the <ESC> key
anytime during the test.
6.2.1.5 Memory Error Detection
During POST memory testing, the detection of single-bit and multi-bit errors in DRAM banks is
enabled. If a single-bit error (SBE) or multiple-bit error (MBE) is detected, the location within a 4K
chunk will be allocated and reported by E7500 MCH and BIOS which will log the error event to
NVRAM. This is done by BIOS automatically. In additional, with multi-bit error, BIOS will stop the
remaining memory test, and record the current test memory as the total memory installed.
If the MBE (Multi-Bit Error) is in the first bank of memory, the system will hang and have no video.
MBE/SBE (Single-Bit Error) errors are handled by SMI handler, When either MBE or SBE errors
are generated, the SMI will be trigged, and the event will be logged into the Flash Rom (in Some
cases, the MBE may not be logged due to the access area is error. A user can view the event in
the <F2> Setup | Advanced | Event Logging | View Event Log). In addition, the system will hang
after the event is logged if it is a MBE error.
6.2.2

Processors

The BIOS determines the processor stepping, cache size, etc through the CPUID instruction.
The requirements are as follows:
•
All processors in the system must operate at the same frequency and have the same
cache sizes, and the same VID. No mixing of product families supported.
•
Processors run at a fixed speed and cannot be programmed to operate at a lower or
higher speed.
6.2.2.1 Processor Initialization
The SE7500CW2 server board can support up to two Intel® Xeon™ processor with 512KB L2
Cache processors. The system BIOS must perform the various initialization sequences to
program each processor cache, APIC and MTRRs.
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Revision 1.40
SE7500CW2 Server Board Technical Product Specification
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Pro processor specifications. It is