Revision History - Intel WiFi Link 5100 Design Manual

®
Intel 5100 MCH Chipset

Revision History

Date Revision
July 2008 003
February 2008 002
November 2007 001
Revision Number Descriptions
Revision Associated Life Cycle Milestone
0.0
0.1–0.4
0.5
0.6–0.7
0.7
0.8–0.9
1.0
1.1–1.4
1.5 Qualification Silicon Samples
1.6–1.9
NDA - 2.0
Public - XXXXXX-001
2.1 and up
Note: Rows highlighted in gray are required revisions.
Intel
July 2008
Order Number: 318676-003US
Description
Added the CompactPCI* reference solution
Added Figure 26, Figure 27, and
Updated the supplier information
Updated the TDP value to 25.7 W in
Max config
Initial release
POP L3 Closure
When Needed
Design Win Phase
When Needed
Simulations Complete
When Needed
First Silicon Samples
When Needed
When Needed
First SKU Launch
When Needed
®
5100 Memory Controller Hub Chipset for Communications, Embedded, and Storage Applications
Figure 28
Table 3
Release Information
Initial Documentation - Typically Internal Only
Project Dependent - Typically Internal Only
First, Required Customer Release
Project Dependent
Second, Recommended Customer Release
Project Dependent
Required Customer Release
Project Dependent (Recommended)
Project Dependent
Project Dependent
Required Customer Release - Product Launch
Project Dependent
TDG
5