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Intel LF80537GF0484M - Cpu Core 2 Duo T7400 2.16Ghz Fsb667Mhz 4Mb Fcpga6 Tray Datasheet

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Intel® Core™2 Duo Processors and
Intel® Core™2 Extreme Processors
for Platforms Based on Mobile Intel®
965 Express Chipset Family
Datasheet
January 2008
Document Number: 316745-005

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Summary of Contents for Intel LF80537GF0484M - Cpu Core 2 Duo T7400 2.16Ghz Fsb667Mhz 4Mb Fcpga6 Tray

  • Page 1 Intel® Core™2 Duo Processors and Intel® Core™2 Extreme Processors for Platforms Based on Mobile Intel® 965 Express Chipset Family Datasheet January 2008 Document Number: 316745-005...
  • Page 2 Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. Intel, Pentium, Intel Core, Intel Core 2, Intel SpeedStep and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

  • Page 3: Table Of Contents

    Clock Control and Low Power States ..............11 2.1.1 Core Low Power State Descriptions ............13 2.1.2 Package Low Power State Descriptions ............15 Enhanced Intel SpeedStep® Technology .............. 18 2.2.1 Dynamic FSB Frequency Switching ............19 2.2.2 Intel® Dynamic Acceleration Technology ........... 19 Extended Low Power States ................
  • Page 4 Power Specifications for the Intel Core 2 Duo Processor - Standard Voltage ......77 Power Specifications for the Intel Core 2 Duo Processor - Low Voltage ......78 Power Specifications for the Intel Core 2 Duo Processor - Ultra Low Voltage .....79 Power Specifications for the Intel Core 2 Extreme Processor ...........80 Thermal Diode Interface ....................81...

  • Page 5: Revision History

    May 2007 • Updates — Chapter 1 added Intel® Core™2 Duo processor - Ultra Low Voltage information — Chapter 3 added Table 8 with Intel Core 2 Duo processor - 316745 -002 June 2007 Ultra Low Voltage U7600 and U7500 specifications —...
  • Page 6 Datasheet...

  • Page 7: Introduction

    • Intel Core 2 Extreme processor Note: In this document, the Intel Core 2 Duo and Intel Core 2 Extreme processors are referred to as the processor and Mobile Intel® 965 Express Chipset family is referred to as the (G)MCH.

  • Page 8: Terminology

    Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ AGTL+ signaling technology on some Intel processors. Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.

  • Page 9: References

    Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669 NOTES: Contact your local Intel representative for the latest revision of this document. § Datasheet...
  • Page 10 Introduction Datasheet...

  • Page 11: Low Power Features

    Low Power Features Low Power Features Clock Control and Low Power States The processor supports low power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states.

  • Page 12: Core Low Power States

    † — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4. ‡ — Core C4 state supports the package level Intel Enhanced Deeper Sleep state Ø — P_LVL5 read is issued once the L2 cache is reduced to zero.

  • Page 13: Core Low Power State Descriptions

    Snoop serviced occurs Stop Grant Snoop † — Deeper Sleep includes the Deeper Sleep state and Intel Enhanced Deeper Sleep state. Table 1. Coordination of Core Low Power States at the Package Level Package State Core1 State Core0 State Normal...
  • Page 14 Low Power Features A System Management Interrupt (SMI) handler returns execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A/3B: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state.

  • Page 15: Package Low Power State Descriptions

    Low Power Features 2.1.2 Package Low Power State Descriptions 2.1.2.1 Normal State This is the normal operating state for the processor. The processor remains in the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state.
  • Page 16 Intel Enhanced Deeper Sleep state which is a sub-state of Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely shut down.
  • Page 17 Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions: • The second core is already in C4 and the Intel Enhanced Deeper Sleep state is enabled (as specified in Section 2.1.1.6).

  • Page 18: Enhanced Intel Speedstep® Technology

    • Enhanced thermal management features: — Digital Thermal Sensor and Out of Specification detection — Intel Thermal Monitor 1 in addition to Intel Thermal Monitor 2 in case of unsuccessful Intel Thermal Monitor 2 transition. — Dual core thermal management synchronization.

  • Page 19: Dynamic Fsb Frequency Switching

    • Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via BIOS. When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be active under certain internal conditions. In such a scenario the processor may draw a...

  • Page 20: Fsb Low Power Enhancements

    BIOS configuration is key to reliable, long-term system operation. Not complying with this guideline may affect the long-term reliability of the processor. Enhanced Intel SpeedStep Technology transitions are multistep processes that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states.

  • Page 21: Processor Power Status Indicator (Psi-2) Signal

    Low Power Features consumption allows for leakage current reduction, which results in platform power savings and extended battery life. There is no platform-level change required to support this feature as long as the VR vendor supports the VID-x feature. Processor Power Status Indicator (PSI-2) Signal The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state.
  • Page 22 Low Power Features Datasheet...

  • Page 23: Electrical Specifications

    Electrical Specifications Electrical Specifications Power and Ground Pins For clean, on-chip power distribution, the processor has a large number of V (power) and V (ground) inputs. All power pins must be connected to V power planes while all V pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop.
  • Page 24 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 2 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250...
  • Page 25 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 3 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375...

  • Page 26: Catastrophic Thermal Protection

    Electrical Specifications Table 2. Voltage Identification Definition (Sheet 4 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures.

  • Page 27: Fsb Frequency Select Signals (Bsel[2:0])

    Electrical Specifications FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table Table 3.

  • Page 28: Fsb Pin Groups

    Electrical Specifications Table 4. FSB Pin Groups Signal Group Type Signals Synchronous AGTL+ Common Clock Input BPRI#, DEFER#, PREQ# , RESET#, RS[2:0]#, TRDY# to BCLK[1:0] Synchronous ADS#, BNR#, BPM[3:0]# , BR0#, DBSY#, DRDY#, HIT#, AGTL+ Common Clock I/O to BCLK[1:0] HITM#, LOCK#, PRDY# , DPWR# Signals...

  • Page 29: Cmos Signals

    Electrical Specifications CMOS Signals CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other non- AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than four BCLKs in order for the processor to recognize them.

  • Page 30: Processor Dc Specifications

    Tjunction = 100°C. Care should be taken to read all notes associated with each parameter. Table 6. Voltage and Current Specifications for the Intel Core 2 Duo Processors - Standard Voltage (Sheet 1 of 2) Symbol...
  • Page 31 VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State).

  • Page 32: Voltage And Current Specifications For The Intel Core 2 Duo Processors - Low Voltage

    VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).

  • Page 33: Voltage And Current Specifications For The Intel Core 2 Duo -Ultra Low Voltage Processors

    CC_CORE Processor I requirements in Intel Dynamic Acceleration Technology mode is lesser than Icc in HFM. The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor is lesser than or equal to 350 mV. Table 8. Voltage and Current Specifications for the Intel Core 2 Duo -Ultra Low Voltage...

  • Page 34: Voltage And Current Specifications For The Intel Core 2 Extreme Processors

    VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
  • Page 35 VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).

  • Page 36: Low Voltage And Ultra Low Voltage And Intel Core 2 Extreme Processors

    Figure 3. Active V and I Loadline Intel Core 2 Duo Processors - Standard Voltage, Low Voltage and Ultra Low Voltage and Intel Core 2 Extreme Processors (PSI# Not Asserted) CC-CORE Slope = -2.1 mV/A at package VccSense, VssSense pins.
  • Page 37 Electrical Specifications Figure 4. Deeper Sleep V and I Loadline Intel Core 2 Duo Processors - Standard Voltage and Intel Core 2 Extreme Processors (PSI# Asserted) CC-CORE CC-CORE CC-CORE Slope = -2.1 mV/A at package Slope = -2.1 mV/A at package VccSense, VssSense pins.

  • Page 38: Fsb Differential Bclk Specifications

    Electrical Specifications Figure 5. Deeper Sleep V and I Loadline Intel Core 2 Duo Processor - Low Voltage and Ultra Low Voltage (PSI# Asserted) NOTE: Deeper Sleep mode tolerance depends on VID value. Table 10. FSB Differential BCLK Specifications Symbol...

  • Page 39: Agtl+ Signal Group Dc Specifications

    Electrical Specifications Table 11. AGTL+ Signal Group DC Specifications Symbol Parameter Unit Notes I/O Voltage 1.00 1.05 1.10 GTLREF Reference Voltage 2/3 V Ω Compensation Resistor 27.23 27.5 27.78 COMP Ω Termination Resistor Input High Voltage GTLREF+0.10 +0.10 Input Low Voltage -0.10 GTLREF-0.10 Output High Voltage...

  • Page 40: Cmos Signal Group Dc Specifications

    Electrical Specifications Table 12. CMOS Signal Group DC Specifications Symbol Parameter Unit Notes I/O Voltage 1.00 1.05 1.10 Input High Voltage 0.7*V +0.1 Input Low Voltage -0.10 0.00 0.3*V CMOS Output High Voltage 0.9*V +0.1 Output Low Voltage -0.10 0.1*V Output High Current Output Low Current Input Leakage Current...

  • Page 41: Package Mechanical Specifications And Pin Information

    These specifications assume that a mechanical attach is designed specifically to load one type of processor. Intel also specifies that 15-lbf load limit should not be exceeded on any of Intel’s BGA packages so as to not impact solder joint reliability after reflow. This load limit ensures that impact to the package solder joints due to transient bend, shock, or tensile loading is minimized.

  • Page 42: 4-Mb And Fused 2-Mb Micro-Fcpga Processor Package Drawing (Sheet 1 Of 2)

    Package Mechanical Specifications and Pin Information Figure 6. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) Bottom View op View Front View Side View ø 0.356 ø 0.254 Detail A Datasheet...

  • Page 43: 4-Mb And Fused 2-Mb Micro-Fcpga Processor Package Drawing (Sheet 2 Of 2)

    Package Mechanical Specifications and Pin Information Figure 7. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) 4X 7.00 4X 7.00 4X 5.00 Side View Edge Keep Out Corner Keep Out Zone Zone op View 0.305±0.25 13.97 0.406 1.625 0.254...

  • Page 44: 2-Mb Micro-Fcpga Processor Package Drawing (Sheet 1 Of 2)

    Package Mechanical Specifications and Pin Information Figure 8. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) Bottom View op View Front View Side View ø 0.356 ø 0.254 Detail A Datasheet...

  • Page 45: 2-Mb Micro-Fcpga Processor Package Drawing (Sheet 2 Of 2)

    Package Mechanical Specifications and Pin Information Figure 9. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) 4X 7.00 4X 7.00 Side View 4X 5.00 Edge Keep Out Corner Keep Out Zone Zone op View 0.305±0.25 13.97 0.406 1.625 0.254 6.985 1.625 13.97...
  • Page 46 Package Mechanical Specifications and Pin Information Figure 10. 4-MB and Fused 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) Bottom View op View Front View Detail B Side View ø 0.203 ø 0.071 0.203 Detail A Datasheet...
  • Page 47 Package Mechanical Specifications and Pin Information Figure 11. 4-MB and Fused 2-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) 4X 7.00 4X 7.00 Side View 4X 5.00 Edge Keep Out Corner Keep Out Zone Zone op View 13.97 1.625 6.985 1.625 13.97...
  • Page 48 Package Mechanical Specifications and Pin Information Figure 12. 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) Bottom View op View Front View Detail B Side View ø 0.203 ø 0.071 0.203 Detail A Datasheet...

  • Page 49: Processor Pinout And Pin List

    0.55 Max Allowable Bottom View Component Height Processor Pinout and Pin List Table 14 shows the top view pinout of the Intel Core 2 Duo mobile processor. The pin list, arranged in two different formats, is shown in the following pages. Datasheet...

  • Page 50: The Coordinates Of The Processor Pins As Viewed From The Top Of The Package

    Package Mechanical Specifications and Pin Information Table 14. The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 1 of 2) SMI# FERR# A20M# RSVD INIT# LINT1 DPSLP# IGNNE THERM RESET# RSVD LINT0 TRIP# STPCLK PWRGO RSVD RSVD...

  • Page 51: The Coordinates Of The Processor Pins As Viewed From The Top Of The Package (Sheet 2 Of 2)

    Package Mechanical Specifications and Pin Information Table 15. The Coordinates of the Processor Pins as Viewed from the Top of the Package (Sheet 2 of 2) BCLK[1] BCLK[0] THRMDA TEST6 BSEL[0] BSEL[1] THRMDC VCCA DBR# BSEL[2] TEST1 TEST3 VCCA PROCHO IERR# RSVD DPWR#...
  • Page 52 Package Mechanical Specifications and Pin Information This page is intentionally left blank. Datasheet...

  • Page 53: Pin Listing By Pin Name

    Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name (Sheet 2 of 16) Table 16. Pin Listing by Pin Name (Sheet 1 of 16) Signal Buffer Pin Name Direction Number Type Signal Buffer Pin Name Direction Input/ Number Type...
  • Page 54 Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name Table 16. Pin Listing by Pin Name (Sheet 3 of 16) (Sheet 4 of 16) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type Input/...
  • Page 55 Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name Table 16. Pin Listing by Pin Name (Sheet 5 of 16) (Sheet 6 of 16) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type Input/...
  • Page 56 Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name Table 16. Pin Listing by Pin Name (Sheet 7 of 16) (Sheet 8 of 16) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type Input/...
  • Page 57 Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name Table 16. Pin Listing by Pin Name (Sheet 9 of 16) (Sheet 10 of 16) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type AA13...
  • Page 58 Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name Table 16. Pin Listing by Pin Name (Sheet 11 of 16) (Sheet 12 of 16) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type Power/Other...
  • Page 59 Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name Table 16. Pin Listing by Pin Name (Sheet 13 of 16) (Sheet 14 of 16) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type AC14...

  • Page 60: Pin Listing By Pin Number

    Package Mechanical Specifications and Pin Information Table 16. Pin Listing by Pin Name Table 16. Pin Listing by Pin Name (Sheet 15 of 16) (Sheet 16 of 16) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type Power/Other...
  • Page 61 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number Table 17. Pin Listing by Pin Number (Sheet 2 of 17) (Sheet 3 of 17) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type Power/Other AA16...
  • Page 62 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number Table 17. Pin Listing by Pin Number (Sheet 4 of 17) (Sheet 5 of 17) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type Input/ Input/...
  • Page 63 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number Table 17. Pin Listing by Pin Number (Sheet 6 of 17) (Sheet 7 of 17) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type VID[2] CMOS...
  • Page 64 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number Table 17. Pin Listing by Pin Number (Sheet 8 of 17) (Sheet 9 of 17) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type BSEL[0] CMOS...
  • Page 65 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number Table 17. Pin Listing by Pin Number (Sheet 10 of 17) (Sheet 11 of 17) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type Power/Other Power/Other...
  • Page 66 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number Table 17. Pin Listing by Pin Number (Sheet 12 of 17) (Sheet 13 of 17) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type Power/Other Power/Other...
  • Page 67 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number Table 17. Pin Listing by Pin Number (Sheet 14 of 17) (Sheet 15 of 17) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type Input/ Power/Other...
  • Page 68 Package Mechanical Specifications and Pin Information Table 17. Pin Listing by Pin Number Table 17. Pin Listing by Pin Number (Sheet 16 of 17) (Sheet 17 of 17) Signal Signal Pin Name Direction Pin Name Direction Number Buffer Type Number Buffer Type Input/ Input/...

  • Page 69: Alphabetical Signals Reference

    Package Mechanical Specifications and Pin Information Alphabetical Signals Reference Table 18. Signal Description (Sheet 1 of 7) Name Type Description A[35:3]# (Address) define a 2 -byte physical memory address space. In sub- phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information.
  • Page 70 Package Mechanical Specifications and Pin Information Table 18. Signal Description (Sheet 2 of 7) Name Type Description BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency BSEL[2:0] Output associated with each combination.
  • Page 71 Deep Sleep State to the Deeper Sleep state. In order to return to the Deep DPRSTP# Input Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by the Intel 82801HBM ICH8M I/O Controller Hub based chipset. DPSLP# when asserted on the platform causes the processor to transition from the...
  • Page 72 STPCLK#. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating point when the processor detects an unmasked floating- point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting.
  • Page 73 When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Intel® Pentium® processor. Both signals are asynchronous.
  • Page 74 Package Mechanical Specifications and Pin Information Table 18. Signal Description (Sheet 6 of 7) Name Type Description Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after V and BCLK RESET#...
  • Page 75 Processor core ground node. Input provides isolated power for the internal processor core PLL’s . Input Processor I/O Power Supply. together with V are voltage feedback signals to Intel MVP-6 CC_SENSE SS_SENSE Ω Output that control the 2.1-m loadline at the processor die. It should be used to sense CC_SENSE voltage near the silicon with little noise.
  • Page 76 Package Mechanical Specifications and Pin Information Datasheet...

  • Page 77: Thermal Specifications And Design Considerations

    Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 78: Power Specifications For The Intel Core 2 Duo Processor - Low Voltage

    Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 79: Power Specifications For The Intel Core 2 Duo Processor - Ultra Low Voltage

    Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 80: Thermal Specifications

    Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 81: Thermal Diode

    Contact your external sensor supplier for recommendations. The thermal diode is separate from the Intel Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor.

  • Page 82: Thermal Diode Parameters Using Diode Model

    2, 3, 5 NOTES: Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range.

  • Page 83: Thermal Diode Offset

    2.79 4.52 6.24 Ω NOTES: Intel does not support or recommend operation of the thermal diode under reverse bias. Same as I Table Characterized across a temperature range of 50-100°C. Not 100% tested. Specified by design characterization. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as...

  • Page 84: Intel® Thermal Monitor

    After automatic mode is enabled, the TCC activates only when the internal die temperature reaches the maximum allowed value for operation. When Intel Thermal Monitor 1 is enabled and a high temperature situation exists, the clocks modulates by alternately turning the clocks off and on at a 50% duty cycle.
  • Page 85 Enhanced Intel SpeedStep Technology target frequency point. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC activates immediately independent of the processor temperature.

  • Page 86: Digital Thermal Sensor

    When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3 In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification. 5.1.4...

  • Page 87: Out Of Specification Detection

    PROCHOT#. If PROCHOT# is driven by an external agent when Intel Thermal Monitor 1, Intel Thermal Monitor 2, and Force Intel Thermal Monitor 1 on Intel Thermal Monitor 2 are all enabled, then the processor will still apply only Intel Thermal Monitor 2.

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