Pci 66 Mhz Embedded Topology; Pci 66 Mhz Embedded Table - Intel 41210 Design Manual

PCI-X Layout Guidelines
8.6.4

PCI 66 MHz Embedded Topology

Figure 21
design.
Figure 21. PCI 66 MHz Embedded Topology
Table 13.

PCI 66 MHz Embedded Table

Reference Plane
Board Impedance
Microstrip Trace Spacing
Stripline Trace Spacing
Group Spacing
Breakout
Trace Length 1 TL1: From 41210 Bridge signal Ball
to first junction
Trace Length TL2 between junctions
Trace Length TL_EM1 to TL_EM4 from junction to
embedded devices
Length Matching Requirements
Number of vias
P
42
and Table 13 provide routing details for a topology with an embedded PCI 66 MHz
Parameter
EM1
TL1 TL2
EM2
Routing Guideline for Lower AD Bus
Route over an unbroken ground plane
60 +/- 15%
18 mils center to center
12 mils center to center
Spacing from other groups: 25 mils min, edge to edge
5 mils on 5 mils spacing. Maximum length of breakout
region can be 500 mils.
5.0" max
0.5" min - 3.5" max
2.0" min - 3.0" max
Clocks coming from the clock driver must be length
matched to within 25 mils.
4 vias max.
Intel® 41210 Serial to Parallel PCI Bridge Design Guide
EM3
EM4
B2722 -01