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Board Layout Guidelines
This chapter provides details on adapter card stackup suggestions. It is highly recommended that
signal integrity simulations be run to verify each 41210 Bridge PCB layout especially if it deviates
from the recommendations listed in these design guidelines.
7.1
Adapter Card Topology
The 41210 Bridge will be implemented on PCI-E adapter cards with an eight layer stackup PCB.
The specified impedance range for all adapter card implementations will be 60 +/-15%.
Adjustments will be made for interfaces specified at other impedances.
layer geometries for eight layer boards.
Table 3.
Adapter Card Stack Up, Microstrip and Stripline
Variable
Solder Mask Thickness (mil)
Solder Mask E
Core Thickness (mil)
Core E
Plane Thickness (mil)
Trace Height (mil)
Preg E
Trace Thickness (mil)
Trace Width (mil)
Total Thickness (mil)
Trace Spacing (using
microstrip E2E/C2C)
Trace Spacing (using
stripline E2E/C2C)
Trace Impedance
Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Nominal
Type
(mils)
N/A
0.8
N/A
3.65
r
N/A
2.8
N/A
4.3
r
Power
2.7
Ground
1.35
1
3.5
2
3.5
3
10.5
Microstrip
4.30
Stripline1
4.30
r
Stripline2
4.3
Microstrip
1.75
Stripline
1.4
Microstrip
4.0
Stripline
4.0
FR4
62.0
[12]/[16]
[12]/[16]
Microstrip
60
Stripline
60
Minimum
Maximum
(mils)
(mils)
0.6
1.0
3.65
3.65
3.0
3.2
3.75
4.85
2113 material
2.5
2.9
1.15
1.55
3.3
3.7
The trace height will be determined to
3.3
3.7
achieve a nominal 60 .
9.9
11.1
3.75
4.85
2113 material
3.75
4.85
2113 material
7628 material. Trace height 3 is composed
3.75
4.85
of one piece of 2113 and one piece of
7628.
1.2
2.3
1.2
1.6
2.5
5.5
2.5
5.5
56.0
68.0
51
69
51
69
7
Table 3
defines the typical
Notes
29
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