Adapter Card Stackup - Intel 41210 Design Manual

Board Layout Guidelines
NOTE: Each interface will set the trace spacing based on its signal integrity of differential impedance
requirements. For the purposes of the building the transmission line models, it is assumed the artwork is
very accurate and therefore a constant. Thus, all the variability in the trace spacing is the result of the
tolerances of the trace width.
Figure 15. Adapter Card Stackup
30
Microstrip
Microstrip
Trace
Trace
Width
Spacing
L1 L1
L2 (GND)
L3 L3
L4 (VCC)
L5 (VCC)
L4 L4
L7 (GND)
L8
Stripline
Stripline
Trace Trace
Width
Spacing
Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Microstrip Trace Thickness
Solder Mask Thickness
Trace Height 1
Trace Height 2
Stripline Trace Thickness
Trace Height 3
Core Thickness
Plane Thickness
B1436-01