Jtag; Related Documents; 41210 Bridge Block Diagram - Intel 41210 Design Manual

Introduction
2.5

JTAG

•
Compliant with IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a
2.6

Related Documents

•
Intel® 41210 Serial to Parallel PCI Bridge Design Specification (EDS), Revision 1.0.
•
PCI Express Specification, Revision 1.0, from www.pci-sig.com.
•
PCI Express Design Guide, Revision 0.5
•
PCI Local Bus Specification, Revision 2.3, from www.pci-sig.com.
•
PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, from www.pci-sig.com.
•
IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a
•
System Management Bus Specification, Revision 2.0
Figure 3. 41210 Bridge Block Diagram
12
JTAG
Intel
PCI-Express x8
41210 Bridge
A_PCLKI
Intel® 41210 Serial to Parallel PCI Bridge Design Guide
SMB Bus
A Bus PCI-X 133MHz
fi
A
Bus Arbiter
A
Clock Buffer
B Bus PCI-X 133MHz
B
Bus Arbiter
B
Clock Buffer
B_PCLKI
6 REQ/GNT Pairs
6 A_PCLKO
6 REQ/GNT Pairs
6 B_PCLKO
B2709-01