Intel 41210 Design Manual page 8

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Table 1. Terminology and Definitions (Sheet 2 of 2)
Term
PCB
SSTL_2
JEDEC
Aggressor
Victim
Network
Stub
CRB
Downstream
Upstream
Local memory
DWORD
Flip Chip
Mode
Conversion
PCI-E
8
Prepreg
Example of a Four-Layer Stack
Series Stub Terminated Logic for 2.5 V
Provides standards for the semiconductor industry.
A network that transmits a coupled signal to another network is aggressor network.
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Victim Network
Aggressor Network
A network that receives a coupled cross-talk signal from another network is a victim network.
The trace of a PCB that completes an electrical connection between two or more components.
Branch from a trunk terminating at the pad of an agent.
Customer Reference Board
Downstream refers either to the relative position of an interconnect/system element (Link/
device) as something that is farther from the Root Complex, or to a direction of information
flow, i.e., when information is flowing away from the Root Complex.
Memory subsystem on the Intel XScale
busses.
32-bit data word.
FC-BGA (flip chip-ball grid array) chip packages are designed with processor core flipped up
on the back of the chip, facing away from the PCB. This allows more efficient cooling of the
package.
Mode Conversions are due to imperfections on the interconnect which transform differential
mode voltage to common mode voltage and common mode voltage to differential voltage.
PCI-Express
Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Definition
Printed circuit board.
Layer 1: copper
Example manufacturing process consists of
the following steps:
Layer 2: GND
• Consists of alternating layers of core and
prepreg stacked
Core
• The finished PCB is heated and cured.
Layer 3: VCC15
• The via holes are drilled
Prepreg
Layer 4: copper
• Plating covers holes and outer surfaces
• Etching removes unwanted copper
• Board is tinned, coated with solder mask
and silk screened
®
core DDR SDRAM or Peripheral Bus Interface
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