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3.9.3
Jumper Summary
Table 17.
Jumper Summary
Jumper
J1C1
J1D2
J7B4
J7D1
J9D3
3.9.4
Connector Summary
Table 18.
Connector Summary
Connector
J1D1
J1E1
J1L1, J1M1,
J1M2, J1N1,
J2M1, J2M2
J1R1
J2A1
J2D1
J2D2
J1B1, J5D1,
J5C1
J2E1
J5B1
J7A1
J7B1, J7B2
J7B3
J7C1
J7D2
J9D1
3.9.5
General Purpose Input/Output Header
Table 19, "J2D2 GPIO Header Definition" on page 39
GPIO signals are muxed with the serial port signals. The serial port must be disabled to use the GPIO
signals. These pins corespond to Jumper J2D2.
Table 19.
J2D2 GPIO Header Definition
Pin
1
2
3
Customer Reference Board Manual
JTAG Chain Enable
Disables UART
SM_SCLK to EEPROM, SM_SDTA to EEPROM
16-bit Flash Enable
Buzzer Volume
RJ45 Network Connector for GbE NIC.
RJ11 Dual Serial Port Connector.
SMA connectors
Secondary PCI-X Expansion bus Slot
Secondary PCI-X Expansion bus Slot.
Power header for fan.
GPIO tap-in Header
Test headers
Edge connector for primary PCI Express Bus.
DIMM
PC104 Mod connector.
2
I
C 4 pin connectors.
Secondary PCI-X Expansion Slot Power. Please see
for more details
Test header (empty)
JTAG CPLD Header.
Power header for battery.
Signal
Pin
GND
4
GPIO7
5
GPIO6
6
Intel® IQ80333 I/O Processor
Hardware Reference Section
Description
Description
Section 2.2.2, "Power Requirements"
shows the GPIO signal assignments. The
Signal
GPIO5
GPIO4
GPIO3
Factory Default
1-2
Open
1-2, 3-4
Open
Open
Pin
Signal
7
GPIO2
8
GPIO1
9
GPIO0
39
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