Figure 75. S0-S5-S0 Transition - Intel 815 Design Manual

Power Delivery

Figure 75. S0-S5-S0 Transition

Stop grant cycle
Go_C3 from ICH
Ack_C3 from GMCH
SUS_STAT#
Cycle 1 from GMCH
Cycle 1 from ICH
Cycle 2 from GMCH
Cycle 2 from ICH
150
Vcc3.3sus
RSMRST#
STPCLK#
t18
CPUSLP#
DRAM
DRAM active
t19
t20
PCIRST#
CPURST#
SLP_S3#
SLP_S5#
PWROK
Vcc3.3core
Clocks
Clocks valid
Freq straps
Wake event
t7
DRAM in STR (CKE low)
t11
t21 t23
t25
t26
t8
t22
t9
Clocks invalid
®
Intel 815 Chipset Platform Design Guide
R
t24
DRAM active
t12
t13
t17
Clocks valid
t15 t16
pwr_S0-S5-S0_trans