Motorola DragonBall MC68328 User Manual page 94

15 14 13 12
POLARITY
POL7 POL6 POL5 POL4
Address: $FFFFF41C
Figure 7-12. Port D INT Enable/Polarity Register
15 14 13 12
0 0 0 0
Address: $FFFFF41E
DIRECTION- DIR[7:0]
These bits control the pin directions. While high, the pins are outputs; while low, the pins
are inputs. Because there are no SELECT bits associated with this port, the I/O function
is always enabled.
DATA- D[7:0]
These bits control or report the data on the pins. While the DIRECTION bits are high, DA-
TA[7:0] controls the data to the pins. While the DIRECTION bits are low, DATA[7:0] re-
ports the signal driving the pins. These bits reset to 0 while the DIRECTION bits are low.
The data bits may be written at any time. Bits that are configured as inputs will accept the
written data, but the data will not be accessible until the respective pins are configured as
outputs. Note that the actual value on the pin is reported when these bits are read. Bits
that are configured as edge-sensitive interrupts will read 1 when an edge is detected. The
interrupt is cleared by writing 1to the set bits.
PULLUP- PU[7:0]
These bits enable the pullup resistors on the port. While high, the pullup resistors are en-
abled. While low, the pullup resistors are disabled. The pullups are enabled on reset.
POLARITY- POL[7:0]
These bits select the input signal polarity. While high, the input data is inverted before be-
ing presented to the holding register; while low, the data is unchanged. Interrupts are ac-
tive-high (or rising edge) while these bits are low. Interrupts are active-low (or falling edge)
while these bits are high.
INT ENABLE- IQEN[7:0]
These bits allow the interrupts to be presented to the interrupt controller block.
EDGE ENABLE- IQEG[7:0]
These bits, while high, enable edge interrupts. While low, level-sensitive interrupts are se-
lected. The polarity of the edge (rising or falling) is selected by the POLARITY bits.
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
11 10 9
POL3 POL2 POL1
11 10 9
UNUSED
0 0 0
Figure 7-13. Port D INT Edge Register
8 7 6 5
POL0 IQEN7 IQEN6 IQEN5
8 7 6 5
0 IQEG7 IQEG6 IQEG5
Parallel Ports
4 3 2 1
INT ENABLE
IQEN4 IQEN3 IQEN2 IQEN1
Reset Value: $0000
4 3 2 1
INT EDGE
IQEG4 IQEG3 IQEG2 IQEG1
Reset Value: $0000
0
IQEN0
0
IQEG0
7-7