Motorola DragonBall MC68328 User Manual page 114

Integrated processor
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TX AVAIL
Transmit FIFO Has A Slot Available
This bit indicates that the transmit FIFO has at least one slot available for data.
0 = Transmitter does not need data
1 = Transmitter needs data
SEND BREAK
This bit forces the transmitter to send a BREAK character. The transmitter will finish send-
ing the character in progress (if any), then send BREAK until this bit is reset. Users are
responsible to ensure that this bit is high for a sufficient period of time to generate a valid
BREAK. Users can continue to fill the FIFO and any characters remaining will be trans-
mitted when the BREAK is terminated.
0 = Do not send break
1 = Send break (continuous 0's)
IGNORE CTS
This bit, while high, forces the CTS signal presented to the transmitter to always be as-
serted, effectively ignoring the external pin. While in this mode, the CTS pin can serve as
a general-purpose input.
0 = Transmit only while CTS pin is asserted
1 = Ignore CTS pin
CTS STATUS
This bit indicates the current status of the CTS pin. A "snapshot" of the pin is taken imme-
diately before this bit is presented to the data bus. While IGNORE CTS is high, this bit can
serve as a general-purpose input.
0 = CTS pin is low
1 = CTS pin is high
CTS DELTA
While high, this bit indicates that the CTS pin changed state and generates a maskable
interrupt. The current state of the CTS pin is available on the CTS STATUS bit. Users can
generate an immediate interrupt by setting this bit high. This feature is useful for software
debugging. The CTS interrupt is cleared by writing 0 to this bit.
0 = CTS pin did not change state since last cleared
1 = CTS pin changed state
MOTOROLA
MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
UART
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