Motorola DragonBall MC68328 User Manual page 51

Phase-Locked Loop and Power Control
a DMA access is in progress, the CPU will wait until the DMA controller has completed its
access before interrupt processing begins.
Figure 3-5 describes the power controller operation. In this example, the clock bursts at
about 15% duty cycle, so the MC68EC000 is active about 15% of the time. The remainder
of the time, the MC68EC000 is in sleep mode. When a wakeup event occurs, the clock
immediately restarts so the processor can service the wakeup event interrupt. The power-
controller burst period is 31 CLK32 periods, or approximately 1 msec. Note that the LCD
DMA controller has access to the bus at all times and the SYSCLK—master clock to all
peripherals— is continuously active.
SYSCLK
CPUCLK
3-6 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
MPU Interface
BURST WIDTH
CLK32
CONTROL
Figure 3-4. Power Control Module
1 msec
Figure 3-5. Power Control Operation
CLOCK
CLK68K
CONTROL
MOTOROLA