Motorola DragonBall MC68328 User Manual page 130

LOAD
This bit forces a new period. It loads the period and width registers and automatically
clears itself after the load has been performed. For slow PCLK periods, the actual load
may occur some time after the MPU writes this bit as the load occurs on the next rising
PCLK edge.
PIN
This bit indicates the current status of the PWM output pin and can change immediately
after it is read, depending on the current state of the pin.
0 = PWM output is low
1 = PWM output is high
POL
This bit controls the PWM output pin polarity. Normally, the output pin is set high at period
boundaries and goes low when a width-compare event occurs.
0 = Normal polarity
1 = Inverted polarity
PWMEN
This bit enables the PWM. While disabled, the PWM is in low-power mode and the pres-
caler does not count. The output pin is forced to 1 or 0 depending on the setting of the
POL bit.
0 = PWM disabled
• The clock prescaler is reset and frozen.
• The counter is reset to 0001 and frozen.
• The contents of the width and period registers are loaded into the comparators.
• The comparators are disabled.
Disabling the PWM may cause a ''glitch'' on the output, depending on the current state of
the counter.
1 = PWM enabled
When this bit is set high, the PWM is enabled and begins a new period. The following ac-
tions occur:
• The output pin changes state to start a new period.
• The clock prescaler is released and begins counting.
• The counter begins counting.
• The comparators are enabled.
• The IRQ bit is set indicating the start of a new period if IRQEN is set.
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
Pulse Width Modulator
11-3