Motorola DragonBall MC68328 User Manual page 24

Table 1-3. Programmer's Memory Map (Continued)
Address Name
Base+$906 UTX
Base+$908 UMISC
Base+$A00 LSSA
Base+$A05 LVPW
Base+$A08 LXMAX
Base+$A0A LYMAX
Base+$A18 LCXP
Base+$A1A LCYP
Base+$A1C LCWCH
Base+$A1F LBLKC
Base+$A20 LPICF
Base+$A21 LPOLCF
Base+$A23 LACDRC
Base+$A25 LPXCD
Base+$A27 LCKCON
Base+$A29 LLBAR
Base+$A2B LOTCR
Base+$A2D LPOSR
Base+$A31 LFRCM
Base+$A32 LGPMR
Base+$B00 HMSR
Base+$B04 ALARM
Base+$B0C CTL
Base+$B0E ISR
Base+$B10 IENR
Base+$B12 STPWCH
The base is $FFFFF000 and $FFF000 from reset. If the double-
mapped bit is cleared in the SCR, then the base is $FFFFF000.
Do not access any space within the 4K register space that is not
defined in the above table. Unpredictable results may occur.
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
Width Block
16 UART
16 UART
32 LCDC Screen Starting Address Register
8 LCDC
16 LCDC
16 LCDC
16 LCDC
16 LCDC
16 LCDC Cursor Width & Height Register
8 LCDC
8 LCDC Panel Interface Config Register
8 LCDC
8 LCDC ACD (M) Rate Control Register
8 LCDC Pixel Clock Divider Register
8 LCDC
8 LCDC Last Buffer Address Register
8 LCDC Octet Terminal Count Register
8 LCDC
8 LCDC Frame Rate Control Modulation Register
16 LCDC Gray Palette Mapping Register
32 RTC RTC Hours Minutes Seconds Register
32 RTC
8 RTC
8 RTC RTC Interrupt Status Register
8 RTC RTC Interrupt Enable Register
8 RTC
Note
Description
UART TX Register
UART Misc Register
Virtual Page Width Register
Screen Width Register
Screen Height Register
Cursor X Position
Cursor Y Position
Blink Control Register
Polarity Config Register
Clocking Control Register
Panning Offset Register
RTC Alarm Register
RTC Control Register
Stopwatch Minutes
Overview
Reset Value(hex)
$0000
$0000
$00000000
$FF
$03FF
$01FF
$0000
$0000
$0101
$7F
$00
$00
$00
$00
$40
$3E
$3F
$00
$B9
$1073
-
$00000000
$00000000
-
$00
$00
$00
$00
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