Omron CP1E Series User Manual page 9

Cp1e cpu unit hardware
Table of Contents

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Section
Section 11 Quick-response Inputs
Section 12 Interrupts
Section 13 High-speed Counters
Section 14 Pulse Outputs
Section 15 PWM Outputs
Section 16 Serial Communications
Section 17 Built-in Functions
Section 18 Operating the Program-
ming Device
Section 19 CPU Unit Cycle Time
Appendices
CP1E CPU Unit Instructions Reference Manual(Cat. No. W483)
Section
Section 1 Summary of Instructions
Section 2 Instruction
Section 3 Instruction Execution
Times and Number of Steps
Appendices
CP1E CPU Unit Hardware User's Manual(W479)
This section describes the quick-response inputs that can be used to
read signals that are shorter than the cycle time.
This section describes the interrupts that can be used with CP1E PLCs,
including input interrupts and scheduled interrupts.
This section describes the high-speed counter inputs, high-speed
counter interrupts, and the frequency measurement function.
This section describes positioning functions such as trapezoidal control,
jogging, and origin searches.
This section describes the variable-duty-factor pulse (PWM) outputs.
This section describes communications with Programmable Terminals
(PTs) without using communications programming, no-protocol commu-
nications with general components, and connections with a Modbus-
RTU Easy Master, Serial PLC Link, and host computer.
This section describes PID temperature control, analog adjusters, the
minimum cycle time, clock functions, memory management, security
functions, debugging, and other functions.
This section describes basic functions of the CX-Programmer for CP1E,
such as using the CX-Programmer for CP1E to write ladder programs to
control the CP1E CPU Unit, to transfer the programs to the CP1E CPU
Unit, and to debug the programs.
This section describes how to monitor and calculate the cycle time of a
CP1E CPU Unit that can be used in the programs.
The appendices provide lists of programming instructions, the Auxiliary
Area, instruction execution times and number of steps, sample ladder
programming, and a comparison with the CP1L.
This section provides a summary of instructions used with a CP1E CPU
Unit.
This section describes the functions, operands and sample programs of
the instructions that are supported by a CP1E CPU Unit.
This section provides the execution times for all instructions used with a
CP1E CPU Unit.
The appendices provide a list of instructions by Mnemonic and ASCII
code table for the CP1E CPU Unit.
Contents
Contents
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