Toshiba Tecra M4 Maintenance Manual page 81

2 Troubleshooting
Table 2-3 Debug port (Boot mode) error status (3/10)
D port status
(F100h) Initialization of H/W (before DRAM
recognition)
Initialization of PIT channel 1
F101h
Checking DRAM type and size (at
cold boot)
Testing the stack area of SM-RAM
F102h Configuring cache memory
Permission of L1/L2 cache
memory
Checking the access of a CMOS
(Only in Cold Boot)
Examining the battery level of
CMOS
Checksum check of CMOS
Initializing data in CMOS (1)
Setting up of IRT status
Storing the size of DRAM
F103h Branch of resuming (only in Cold
Boot)
2-24
Inspection items
[CONFIDENTIAL]
2.4 System board Troubleshooting
Details
Initialization of MCHM
Initialization of ICH6M.D31.Func0
Initialization of ICH6M.D31.Func1
Initialization of ICH6M.D31.Func1/2
Initialization of USB controller
Initialization of ICH6M.D31.Func3
Initialization of ICH6 AC97 Audio
Initialization of TI controller
(Setting the refresh interval to "30μs")
When unsupported memory is connected,
the system beeps and halts.
When DRAM size = 0, halts.
When it can not be used as stack area,
halts.
When error is detected, halts
(Setting of boot status and IRT busy flag,
The rest bits are set to 0)
When a CMOS error is detected, it does
not resume.
If "resume status code" is not set, no
resume occurs.
TECRA M4 Maintenance Manual (960-521)