Command/Response - SanDisk SDSDB-32-201-80 - Industrial Grade Flash Memory Card Product Manual

All timing values are defined in Table 5-5. The host must keep the clock running for at least N
the card response is received. This restriction applied to command and data response tokens.

5.4.1. Command/Response

Host Command to Card Response Card is Ready
CS H H L L L
<-N ->
CS
DataIN
X X H H H H 6 Bytes Command H H H H H
DataOut Z Z Z H H H H * * * * * * * * H H H H H
Figure 5-11. Host Command to Card Response Card is Ready
Host Command to Card Response Card is Busy
The following timing diagram describes the command response transaction for commands when the card responses
which the R1b response type (e.g., SET_WRITE_PROT and ERASE). When the card is signaling busy, the host
may deselect it (by raising the CS) at any time. The card will release the DataOut line one clock after the CS going
high. To check if the card is still busy it needs to be reselected by asserting (set to low) the CS signal. The card will
resume busy signal (pulling DataOut low) one clock after the falling edge of CS.
CS H L L L
<-N ->
CS
DataIN
X H H H H 6 Bytes Command H H H H H H H H H H H H H X X X H H H H H H X X
DataOut Z Z H H H H
Figure 5-12. Host Command to Card Response Card is Busy
Card Response to Host Command
CS L L L L L
DataIN H H H H H H * * * * * * * * * * * * * H H H H
DataOut H H H H H 1 or 2 Bytes Response H H H H
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION
Table 5-4. SPI Bus Timing Abbreviations
H Signal is high (logical '1')
L Signal is low (logical '0')
X Don't care
Z High impedance state (-> = 1)
* Repeater
Busy Busy Token
Command Command token
Response Response token
Data block Data token
* * * * * * * * * * * * * * * * * * *
<-N ->
CR
* * * * * * * * * * * * * * * * * * *
<-N ->
CR
* * * * * * * * H H H H Card Response
* * * * * * * * * * * * * * * * * * *
<-N ->
CR
Figure 5-13. Card Response to Host Command
* * * * * * * * * * * * * * *
1 or 2 Bytes Response
L L L L H H H L L L L L L H H
<-N -> <-N ->
EC DS
Busy L Z Z Z Busy H H H H Z
6 Bytes Command
* * * * * * * * * * * * * * * * *
SPI Protocol Definition
clock cycles after
CR
L L L L H H H
<-N ->
EC
H H H H X X X
H H H H H Z Z
<-N ->
EC
L L H H H H
H H H X X X X
H H H H Z Z Z
5-17