Data Read - SanDisk SDSDB-32-201-80 - Industrial Grade Flash Memory Card Product Manual

Secure Digital (SD) Card Protocol Description
<------Host command ---->
CMD S T content
Figure 4-12. Identification Timing (Card Identification Mode)
Assign a card relative address
The SEND_RELATIVE_ADDR (CMD 3) for SD Card timing is given bellow. Note that CMD3 command's
content, functionality and timing are different for MultiMediaCard. The minimum delay between the host command
and card response is N clock cycles.
CR
<---- Host command ---->
CMD S T content
Data transfer mode
After the card published it own RCA it will switch to data transfer mode. The command is followed by a period of
two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card.
This timing diagram is relevant for all responded host commands except and ACMD41 and CMD2.
<---- Host command ----> <-N
CMD S T content
Figure 4-13. Command Response Timing (Data Transfer Mode)
Last Card Response—Next Host Command Timing
After receiving the last card response, the host can start the next command transmission after at least N
cycles. This timing is relevant for any host command.
<-------- Response -------->
CMD S T content
Figure 4-14. Timing Response End to Next CMD Start (Data Transfer Mode)
Last Host Command—Next Host Command Timing
After the last command has been sent, the host can continue sending the next command after at least N
periods.
<----- Host command ---->
CMD S T content

4.11.2. Data Read

Note that the DAT line represents the data bus (either 1 or 4 bits).
Single Block Read
The host selects one card for data read operation by CMD7, and sets the valid block length for block oriented data
transfer by CMD16. The basic bus timing for a read operation is given in Figure 5-17. The sequence starts with a
single block read command (CMD17) which specifies the start address in the argument field. The response is sent
on the CMD line as usual.
4-28
<-N cycles ->
ID
CRC E Z Z P * * * P S T
<-N cycles->
CR
CRC E Z Z P * * * P S T
Figure 4-13 SEND_RELATIVE_ADDR Timing
cycles-> <-------- Response --------->
CR
CRC E Z Z P * * * P S T
<-N cycles->
RC
CRC E Z * * * * * *
<-N cycles->
CC
CRC E Z * * * * * *
Figure 4-15. Timing of Command Sequences (All Modes)
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION
<--- CID or OCR --->
content
<-------- Response --------->
content CRC E Z Z Z
content CRC E Z Z Z
<---- Host command ----->
Z S T content CRC E
<---- Host command ----->
Z S T content CRC E
Z Z Z
clock
RC
clock
CC