Timing Values; Spi Electrical Interface; Spi Bus Operating Conditions; Bus Timing - SanDisk SDSDB-32-201-80 - Industrial Grade Flash Memory Card Product Manual

The following figure describes stop transmission operation in Multiple Block Write transfer.
CS L L L L L L L L L L L L L L L L L L L L L L H H H L L L L
Data In Data Block H H H H H H H H H stop tran
Data Out H H H H Data Resp Busy
(1) The Busy may appear within N
command.
Figure 5-18. Stop Transmission Timing—Multiple Block Write

5.4.4. Timing Values

Table 5-5 shows the timing values and definitions. For more information, refer to Table 4-17 in Section 4.0,
Section 5.1.9.2, and the applications note in Appendix A, "Host Design Considerations: NAND MMC and SD-
based Products."
NOTE: min [{{(TAAC f) + (NSAC
frequency.

5.5. SPI Electrical Interface

The SPI Mode electrical interface is identical to that of the SD Card mode.

5.6. SPI Bus Operating Conditions

Identical to SD Card mode.

5.7. Bus Timing

Identical to SD Card mode. The timing of the CS signal is the same as any other card input.
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION
<N -> <1byte-> <N
WR
token
H H H H H H H H H Busy
clocks after Stop Tran Token. If there is no Busy, the host may continue to the next
BR
Table 5-5. Timing Constants Definitions
Min
N 0
CS
N 0
CR
N 1
RC
N 1
AC
N 1
WR
N 0
EC
N 0
DS
N 0
BR
100)} 1/8}, {(100ms * f) * 1/8}] where units = (8 clocks) and "f" is the clock
-> <N -> <- N ->
BR EC DS
H H H X X X H H H H
L Z Z Z Busy
(1)
Max Unit
- 8 Clock Cycles
8 8 Clock Cycles
- 8 Clock Cycles
See Note 8 Clock Cycles
- 8 Clock Cycles
- 8 Clock Cycles
- 8 Clock Cycles
1 8 Clock Cycles
SPI Protocol Definition
H
(1)
5-19