Spi Bus Timing Diagrams; Command/Response - SanDisk SDMB-16-470 - 16 MB MultiMedia Card Product Manual

6.4

SPI Bus Timing Diagrams

All timing diagrams use the following schematics and abbreviations:
All timing values are defined in Table 6-2. The host must keep the clock running for at least N
cycles after the card response is received. This restrictions applied to command and data response
tokens.
6.4.1

Command/Response

Host Command to Card Response - Card is Ready
Host Command to Card Response - Card is Busy
SanDisk MultiMediaCard Product Manual Rev. 2 © 2000 SANDISK CORPORATION
H Signal is high (logical '1')
L Signal is low (logical '0')
X
Z high impedance state (-> = 1)
*
Busy
Command
Response
Data block
MultiMediaCard Product Manual
Don't care
repeater
Busy Token
Command token
Response token
Data token
clock
CR
71