Reset Sequence; Clock Control - SanDisk SDSDB-32-201-80 - Industrial Grade Flash Memory Card Product Manual

SPI Protocol Definition
The data time out for the CSD command cannot be set to the card TAAC since this value is stored in the CSD.
Therefore, the standard response time-out value (N ) is used for read latency of the CSD register.
CR

5.1.7. Reset Sequence

The SD Card requires a defined reset sequence. After power on reset or CMD0 (software reset), the card enters an
idle state. At this state, the only legal host commands are CMD1 (SEND_OP_COND), ACMD41
(SD_SEND_OP_COND), CMD59 (CRC_ON_OFF) and CMD58 (READ_OCR).
The host must poll the card (by repeatedly sending CMD1) until the 'in-idle-state' bit in the card response indicates
(by being set to 0) that the card completed its initialization processes and is ready for the next command.
In SPI mode, however, CMD1 has no operands and does not return the contents of the OCR register. Instead, the
host can use CMD58 (SPI Mode Only) to read the OCR register. It is the responsibility of the host to refrain from
accessing cards that do not support its voltage range.
The use of CMD58 is not restricted to the initialization phase only, but can be issued at any time. The host must poll
the card (by repeatedly sending CMD1) until the 'in-idle-state' bit in the card response indicates (by being set to 0)
that the card has completed its initialization process and is ready for the next command.

5.1.8. Clock Control

The SPI bus clock signal can be used by the SPI host to set the cards to energy-saving mode or to control the data
flow (to avoid under-run or over-run conditions) on the bus. The host is allowed to change the clock frequency or
shut it down.
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION 5-5