SanDisk SDSDB-32-201-80 - Industrial Grade Flash Memory Card Product Manual page 76

Secure Digital (SD) Card Protocol Description
Bits 45:40 indicate the index of the command to which it is responding. The status of the card is coded in 32 bits.
Note that when a data transfer to the card is involved, a busy signal may appear on the data line after the
transmission of each block of data. The host will check for busy after the data block transmission.
Bit Position 47
Width (bits) 1
Value '0'
Description start bit
R1b is identical to R1 with an optional busy signal transmitted on the data line. The card may become busy after
receiving these commands based on its state prior to the command reception. The host will check for busy at the
response.
R2 (CID, CSD register): response length 136 bits.
The content of the CID register is sent as a response to CMD2 and CMD10. The content of the CSD register is sent
as a response to CMD9. Only bits [127...1] of the CID and CSD are transferred, bit [0] of these registers is replaced
by the end bit of the response.
Bit Position
Width (bits)
Value
Description start bit
R3 (OCR register): response length 48 bits.
The contents of the OCR register are sent as a response to ACMD41.
Bit Position 47
Width (bits) 1
Value '0'
Description start bit
R4 and R5: responses are not supported.
R6 (Published RCA response): code length 48-bit. The bits 45:40 indicate the index of the command to be
responded to—in that case it will be '000011' (together with bit 5 in the status bits it means = CMD3). The 16 MSB
bits of the argument field are used for the published RCA number.
4-26
Table 4-12. Response R1
46
1
'0'
transmission bit command index
Table 4-13. Response R2
135 134
1 1
'0' '0'
transmission bit
Table 4-14. Response R3
46
1
'0'
transmission bit
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION
[45:40] [39:8]
6 32
x x
card status
[133:128] [127:1]
6 127
'111111'
reserved CID or CSD register incl.
internal CRC7
[45:40] [39:8]
6 32
'111111' x
reserved OCR register
[7:1] 0
7 1
x '1'
CRC7 end bit
0
1
x '1'
end bit
[7:1]
7
'1111111'
reserved
0
1
'1'
end bit