Cyclic Redundancy Codes (Crc) - SanDisk SDSDB-32-201-80 - Industrial Grade Flash Memory Card Product Manual

1) CLK
CMD
(ACMD41)
2) CLK
CMD
(ACMD41)
It is an obvious requirement that the clock must be running for the SD Card to output data or response
tokens. After the last SD Card bus transaction, the host is required to provide eight (8) clock cycles for
the card to complete the operation before shutting down the clock. Following is a list of various SD
Card bus transactions:
A command with no response—eight clocks after the host command end bit.
A command with response—eight clocks after the card response end bit.
A read data transaction—eight clocks after the end bit of the last data block.
A write data transaction—eight clocks after the CRC status token.
The host is allowed to shut down the clock of a "busy" card. The SD Card will complete the
programming operation regardless of the host clock. However, the host must provide a clock edge for
the card to turn off its busy signal. Without a clock edge the SD Card (unless previously disconnected
by a deselect command -CMD7) will force the DAT0 line down, permanently.

4.6. Cyclic Redundancy Codes (CRC)

The Cyclic Redundancy Check (CRC) is intended for protecting SD Card commands, responses and data transfer
against transmission errors on the SD Card bus. One CRC is generated for every command and checked for every
response on the CMD line. For data blocks, CRC is generated for each DAT line per transferred block. The CRC is
generated and checked as described in the following:
CRC7
The CRC7 check is used for all commands, for all responses except type R3, and for the CSD and CID registers.
The CRC7 is a 7-bit value and is computed as follows:
generator polynomial: G(x) = x
M(x) = (first bit) * x
CRC[6...0] = Remainder [(M(x) * x
The first bit is the most significant bit of the corresponding bit string (of the command, response, CID or CSD). The
degree n of the polynomial is the number of CRC protected bits decreased by one. The number of bits to be
protected is 40 for commands and responses (n = 39), and 120 for the CSD and CID (n = 119).
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION
100KHz-400KHz Clocks
1st
Polling less than 50ms interval
<50ms
1st
Figure 4-9. Host Procedures Waiting for Card to be Ready
7 3
+ x + 1.
n n-1
+ (second bit) * x +...+ (last bit) * x
7
) / G(x)]
Secure Digital (SD) Card Protocol Description
2nd
<50ms
2nd
0
3rd
3rd
4-15