Data Read; Data Write - SanDisk SDSDB-32-201-80 - Industrial Grade Flash Memory Card Product Manual

SPI Protocol Definition

5.4.2. Data Read

The following timing diagram describes all single block read operations with the exception of SEND_CSD
command.
CS
H L L L
<-N ->
CS
DataIN X H H H H Read Command
DataOut
Z Z H H H H
The following table describes Stop transmission operation in case of Multiple Block Read.
L L L L
CS
<- NCS ->
X H H H H
DataIN
Data Transfer to host
DataOut
Reading the CSD Register
The following timing diagram describes the SEND_CSD command bus transaction. The timeout values for the
response and the data block are N
H L L L
CS
<- N ->
CS
X H H H H
DataIN
Z Z H H H H
DataOut

5.4.3. Data Write

The host may deselect a card (by raising the CS) at any time during the card busy period (refer to the given timing
diagram). The card will release the DataOut line one clock after the CS going high. To check if the card is still busy
it needs to be re-selected by asserting (set to low) the CS signal.
The card will resume busy signal (pulling DataOut low) one clock after the falling edge of CS.
CS H L
<-N ->
CS
DataIN X H H H Write Command H H H H
DataOut Z Z H H H * * * * * * * * H H H Card Resp H H H H H H H Data Resp
5-18
* * * * * * * * * * * * * * * * * * * * * * * * * * * *
H H H H H
<-N ->
CR
* * * * * * * * H H H H
Figure 5-14. Single Block Read Timing
* * * * * * * * * * * * * * * * * * * *
Stop Tran command H H H H H
<- NCR ->
<2clk>
Figure 5-15. Multiple Block Read Timing
(Since the N is still unknown).
CR AC
* * * * * * * * * * * * * * * * * * *
Read Command H H H H H
<- N ->
CR
* * * * * * * * H H H H
Figure 5-16. Reading the CSD Register
* * * * * * * * * * * * * * * * * * *
<-N ->
CR
Figure 5-17. Device Write Timing
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION
* * * * * * * * * * * * * * * * * * * * * * * * *
<-N ->
AC
Card Response H H H H Data Block H H H H Z Z Z
* * * * ** * * *
H H Card Response H
* * * * * * * * * * * * * * *
<- N ->
CR
Card Response H H H H
L L L L L L L
<-N ->
WR
H H H Data Block H H H H H H X X X H H H H
L L L H H H H
<-N ->
EC
H H H X X X X
L L L H H H H
<- N ->
EC
H H H X X X X
Data Block H H H H Z Z Z
L H H H L
<-N -> <-N ->
EC DS
Busy L Z Z Z
L L L
Busy H