Interface/Bus Timing; Attribute Memory Read Timing Specification - SanDisk SDP3B Product Manual

SDP3B FlashDisk Product Manual
4.3.5

Interface/Bus Timing

There are two types of bus cycles and timing
sequences that occur in the
interface, a direct mapped I/O transfer and a
memory access. The two timing sequences are
explained in detail in the PCMCIA PC Card
Standard Release 2.1. The SDP3B FlashDisk
conforms to the timing in that reference document.
Table 4-3 Attribute Memory Read Timing
Speed Version
Item
Card Enable Access Time
Output Enable Access Time
Output Disable Time from CE
Output Disable Time from OE
Output Enable Time from CE
Output Enable Time from OE
Data Valid from Address Change
An
-REG
-CE
ten(CE)
-OE
Dout
Notes: All times are in nanoseconds. Dout signifies data provided by the SDP3B FlashDisk to the system. The -CE
signal or both the -OE signal and the -WE signal must be de-asserted between consecutive cycle
operations.
30
PCMCIA type
Read Cycle Time
Address Access Time
Address Setup Time
tsu(A)
ten(OE)
Figure 4-1 Attribute Memory Read Timing Diagram
SanDisk SDP3B FlashDisk Product Manual © 1998 SANDISK CORPORATION
4.3.6 Attribute Memory Read Timing
Specification
The Attribute Memory access time is defined as
300 ns. Detailed timing specifications are shown
in Table 4-3.
Symbol IEEE Symbol
tc(R) tAVAV
ta(A) tAVQV
ta(CE) tELQV
ta(OE) tGLQV
tdis(CE) tEHQZ
tdis(OE) tGHQZ
tsu (A) tAVWL
ten(CE) tELQNZ
ten(OE) tGLQNZ
tv(A) tAXQX
tc(R)
ta(A)
ta(CE)
ta(OE)
300 ns
Min ns. Max ns.
300
300
300
150
100
100
30
5
5
0
tv(A)
tdis(CE)
tdis(OE)