Front Side Bus Signal Groups; Fsb Signal Groups - Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Datasheet

The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
• TESTHI[1:0] - can be grouped together with a single pull-up to V
• TESTHI[7:2] - can be grouped together with a single pull-up to V
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
2.7

Front Side Bus Signal Groups

The FSB signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END as reference levels. In this document, the
term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group
when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as
the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active
anytime and include an active PMOS pull-up transistor to assist during the first clock of
a low-to-high voltage transition.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the
second set is for the source synchronous signals which are relative to their respective
strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals
are still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle.
and asynchronous.
Table 2-6. FSB Signal Groups (Sheet 1 of 2)
Signal Group
AGTL+ Common Clock Input
AGTL+ Common Clock Output
AGTL+ Common Clock I/O
AGTL+ Source Synchronous I/O
AGTL+ Strobes I/O
Open Drain Output
22
Table 2-6 identifies which signals are common clock, source synchronous
Synchronous to
BCLK[1:0]
Synchronous to
BCLK[1:0]
Synchronous to
BCLK[1:0]
Synchronous to assoc.
strobe
Synchronous to
BCLK[1:0]
Asynchronous
Type
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,
TRDY#;
BPM4#, BPM[2:1]#, BPMb[2:1]#
ADS#, AP[1:0]#, BINIT#
BPM3#, BPM0#, BPMb3#, BPMb0#, BR[1:0]#,
DBSY#, DP[3:0]#, DRDY#, HIT#
LOCK#, MCERR#
Signals
REQ[4:0]#,A[16:3]#,
3
A[37:36]#
A[35:17]#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
FERR#/PBE#, IERR#, PROCHOT#, THERMTRIP#
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Electrical Specifications
TT
TT
1
Signals
2 2
, BNR# , BPM5#,
2 2
, HITM# ,
2
Associated Strobe
ADSTB0#
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#