Agtl+ Signal Description Table; Non Agtl+ Signal Description Table - Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Datasheet

Electrical Specifications
Table 2-6. FSB Signal Groups (Sheet 2 of 2)
Signal Group
CMOS Asynchronous Input
CMOS Asynchronous Output
FSB Clock
TAP Input
TAP Output
Power/Other
Notes:
1. Refer to
2. These signals may be driven simultaneously by multiple agents (Wired-OR).
3. Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#.
Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300
Series Specification Update.
Table 2-7
Table 2-7
open drain signals.
Table 2-7.

AGTL+ Signal Description Table

1
A[37:3]#
BINIT#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
Note:
1. Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#.
Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300
Series Specification Update.
Table 2-8.

Non AGTL+ Signal Description Table

FORCEPR#
Note:
1. Signals that have a 50 Ω pullup to V
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Asynchronous
Asynchronous
Clock
Synchronous to TCK
Synchronous to TCK
Power/Other
Section 5 for signal descriptions.
and Table 2-8 outline the signals which include on-die termination (R
denotes AGTL+ signals, while
Table 2-9 provides signal reference voltages.
AGTL+ signals with R
TT
, ADS#, ADSTB[1:0]#, AP[1:0]#,
Signals with R
TT
1 1
, PROCHOT#
Type
A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, PWRGOOD, SMI#, STPCLK#,
BSEL[2:0], VID[6:1]
BCLK[1:0]
TCK, TDI, TMS, TRST#
TDO
COMP[3:0], GTLREF_ADD_MID,
GTLREF_ADD_END, GTLREF_DATA_MID,
GTLREF_DATA_END, LL_ID[1:0], MS_ID[1:0],
PECI, RESERVED, SKTOCC#, TESTHI[11:10],
TESTHI[7:0], TESTIN1, TESTIN2, VCC,
VCC_DIE_SENSE, VCC_DIE_SENSE2, VCCPLL,
VID_SELECT, VSS_DIE_SENSE,
VSS_DIE_SENSE2, VSS, VTT, VTT_OUT,
VTT_SEL
Table 2-8 outlines non AGTL+ signals including
AGTL+ signals with no R
BPM[5:0]#, BPMb[3:0]#, RESET#, BR[1:0]#
A20M#, BCLK[1:0], BSEL[2:0], COMP[3:0], FERR#/
PBE#, GTLREF_ADD_MID, GTLREF_ADD_END,
GTLREF_DATA_MID, GTLREF_DATA_END, IERR#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, LL_ID[1:0],
MS_ID[1:0], PECI, PWRGOOD, SKTOCC#, SMI#,
STPCLK#, TCK, TDI, TDO, TESTHI[11:10], TESTHI[7:0],
TESTIN1, TESTIN2, THERMTRIP#, TMS, TRST#,
VCC_DIE_SENSE, VCC_DIE_SENSE2, VID[6:1],
VID_SELECT, VSS_DIE_SENSE, VSS_DIE_SENSE2,
VTT_SEL
on package.
TT
1
Signals
TT
TT
Signals with no R
TT
).
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