Front Side Bus Low Power Enhancements; Processor Power Status Indicator (Psi#) Signal - Intel RH80536GC0332M - Pentium M 1.8 GHz Processor Datasheet

Pentium m processor on 90 nm process with 2-mb l2 cache

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2.3

Front Side Bus Low Power Enhancements

The Pentium M processor incorporates the following front side bus (processor system bus) low

power enhancements:

•

Dynamic FSB Power Down

•

BPRI# control for address and control input buffers

•

Dynamic On Die Termination disabling

•

Low VCCP (I/O termination voltage)

The Pentium M processor incorporates the DPWR# signal that controls the data bus input buffers

on the processor. The DPWR# signal disables the buffers when not used and activates them only

when data bus activity occurs, resulting in significant power savings with no performance impact.

BPRI# control also allows the processor address and control input buffers to be turned off when the

BPRI# signal is inactive. The on-die termination on the processor FSB buffers is disabled when the

signals are driven low, resulting in additional power savings. The low I/O termination voltage is on

a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all

times.

2.4

The Pentium M processor incorporates the PSI# signal that is asserted when the processor is in a

low power (Deep Sleep or Deeper Sleep) state. This signal is asserted upon Deep Sleep entry and

deasserted upon exit. PSI# can be used to improve the light load efficiency of the voltage regulator,

resulting in platform power savings and extended battery life. PSI# can also be used to simplify

voltage regulator designs since it removes the need for integrated 100 μs timers required to mask

the PWRGOOD signal during Deeper Sleep transitions. It also helps loosen PWRGOOD

monitoring requirements in the Deeper Sleep state.

Datasheet

Low Power Features

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