Features; Power-On Configuration Options; Clock Control And Low Power States; Power-On Configuration Option Lands - Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Datasheet

Features

7
Features
7.1

Power-On Configuration Options

Several configuration options can be configured by hardware. Quad-Core Intel® Xeon®
Processor 5300 Series sample its hardware configuration at reset, on the active-to-
inactive transition of RESET#. For specifics on these options, please refer to
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor, for reset purposes, the processor does not distinguish between a "warm"
reset (PWRGOOD signal remains asserted) and a "power-on" reset.
Table 7-1.

Power-On Configuration Option Lands

Output tri state
Execute BIST (Built-In Self Test)
Disable MCERR# observation
Disable BINIT# observation
Symmetric agent arbitration ID
Notes:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address lands not identified in this table as configuration options should not be asserted during RESET#.
3. Requires de-assertion of PWRGOOD.
Disabling of any of the cores within the Quad-Core Intel® Xeon® Processor 5300
Series must be handled by configuring the EXT_CONFIG Model Specific Register (MSR).
This MSR will allow for the disabling of a single core per die within the Quad-Core
Intel® Xeon® Processor 5300 Series package. Additional details can be found in the
Intel® 64 and IA-32 Architecture Software Developer's Manual.
7.2

Clock Control and Low Power States

Quad-Core Intel® Xeon® Processor 5300 Series support the Extended HALT state (also
referred to as C1E) in addition to the HALT state and Stop-Grant state to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See
power states. The Extended HALT state is a lower power state than the HALT state or
Stop Grant state.
The Extended HALT state must be enabled via the BIOS for the processor to
remain within its specifications. Refer to the Intel® 64 and IA-32 Architecture
Software Developer's Manual. For processors that are already running at the lowest bus
to core frequency ratio for its nominal operating point, the processor will transition to
the HALT state instead of the Extended HALT state.
The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In
a multiprocessor system, all the STPCLK# signals are bussed together, thus all
processors are affected in unison. When the STPCLK# signal is asserted, the processor
enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each
processor. The chipset needs to account for a variable number of processors asserting
the Stop Grant SBC on the bus before allowing the processor to be transitioned into one
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Configuration Option
Figure 7-1
Land Name
SMI#
A3#
A9#
A10#
BR[1:0]#
for a visual representation of the processor low
Table 7-1.
Notes
1,2,3
1,2
1,2
1,2
1,2
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