Front Side Bus Signal Groups; Fsb Signal Groups - Intel E5205 - Cpu Xeon 1.86Ghz Fsb1066Mhz 6M Lga771 Dual Core Tray Datasheet

The TESTHI signals must use individual pull-up resistors as detailed below. A matched
resistor must be used for each signal:
• TESTHI8 - cannot be grouped with other TESTHI signals
• TESTHI9 - cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI12 - cannot be grouped with other TESTHI signals
2.7

Front Side Bus Signal Groups

The FSB signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF_DATA and GTLREF_ADD as reference
levels. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the
AGTL+ output group as well as the AGTL+ I/O group when driving. AGTL+
asynchronous outputs can become active anytime and include an active PMOS pull-up
transistor to assist during the first clock of a low-to-high voltage transition.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, and so forth) and
the second set is for the source synchronous signals which are relative to their
respective strobe lines (data and address) as well as rising edge of BCLK0.
Asynchronous signals are still present (A20M#, IGNNE#, and so forth) and can become
active at any time during the clock cycle.
clock, source synchronous and asynchronous.
Table 2-6. FSB Signal Groups (Sheet 1 of 2)
Signal Group
AGTL+ Common Clock Input
AGTL+ Common Clock Output
AGTL+ Common Clock I/O
AGTL+ Source Synchronous
I/O
AGTL+ Strobes I/O
Open Drain Output
22
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications
Table 2-6
Type
Synchronous to
BCLK[1:0]
Synchronous to
BCLK[1:0]
Synchronous to
BCLK[1:0]
Synchronous to assoc.
strobe
Synchronous to
BCLK[1:0]
Asynchronous
identifies which signals are common
1
Signals
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,
TRDY#;
BPM4#, BPM[2:1]#
2
ADS#, AP[1:0]#, BINIT# , BNR#
BPM3#, BPM0#, BR[1:0]#, DBSY#, DP[3:0]#,
2 2
DRDY#, HIT# , HITM# , LOCK#, MCERR#
Signals Associated Strobe
REQ[4:0]#,A[16:3]#, ADSTB0#
A[37:36]#
A[35:17]# ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
FERR#/PBE#, IERR#, PROCHOT#,
THERMTRIP#, TDO
2
, BPM5#,
2