Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Datasheet page 77

Signal Definitions
Table 5-1. Signal Definitions (Sheet 7 of 8)
Name Type
TESTHI[11:10]
I
TESTHI[7:0],
TESTIN1 I
TESTIN2 I
THERMTRIP# O
TMS I
TRDY# I
TRST# I
V I
CCPLL
VCC_DIE_SENSE O
VCC_DIE_SENSE2
VID[6:1] O
VID_SELECT O
VSS_DIE_SENSE O
VSS_DIE_SENSE2
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
TESTHI[11:10] and TESTHI[7:0],must be connected to a V
resistor for proper processor operation. Refer to
restrictions.
TESTIN1 must be connected to a VTT power source through a resistor as well as to
the TESTIN2 land of the same socket for proper processor operation.
TESTIN2 must be connected to a VTT power source through a resistor as well as to
the TESTIN1 land of the same socket for proper processor operation.
Refer to Section 2.6 for TESTIN restrictions.
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a temperature beyond which permanent silicon damage
may occur. Measurement of the temperature is accomplished through an internal
thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal
clocks (thus halting program execution) in an attempt to reduce the processor
junction temperature. To protect the processor its core voltage (V
removed following the assertion of THERMTRIP#. Intel also recommends the removal
of V when THERMTRIP# is asserted.
TT
Driving of the THERMTRIP# signals is enabled within 10 μs of the assertion of
PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,
THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion
of the PWRGOOD signal will de-assert THERMTRIP#, if the processor's junction
temperature remains at or above the trip level, THERMTRIP# will again be asserted
within 10 μs of the assertion of PWRGOOD.
TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
See the Debug Port Design Guide for Blackford and Greencreek Systems (External
Version) for further information.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a
write or implicit writeback data transfer. TRDY# must connect the appropriate pins of
all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low
during power on Reset.
The Quad-Core Intel® Xeon® Processor 5300 Series implement an on-die PLL filter
solution. The V input is used as a PLL supply voltage.
CCPLL
VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated, low impedance
connection to the processor core power and ground. This signal should be connected
to the voltage regulator feedback signal, which insures the output voltage (that is,
processor voltage) remains within specification. Please see the applicable platform
design guide for implementation details.
VID[6:1] (Voltage ID) pins are used to support automatic selection of power supply
voltages (V ). These are CMOS signals that are driven by the processor and must be
CC
pulled up through a resistor. Conversely, the voltage regulator output must be
disabled prior to the voltage supply for these pins becomes invalid. The VID pins are
needed to support processor voltage specification variations. See
definitions of these pins. The VR must supply the voltage that is requested by these
pins, or disable itself.
VID_SELECT is an output from the processor which selects the appropriate VID table
for the Voltage Regulator. This signal is not connected to the processor die. This signal
is a no-connect on the Quad-Core Intel® Xeon® Processor 5300 Series package.
VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated, low impedance
connection to the processor core power and ground. This signal should be connected
to the voltage regulator feedback signal, which insures the output voltage (that is,
processor voltage) remains within specification. Please see the applicable platform
design guide for implementation details.
Description
power source through a
TT
Section 2.6 for TESTHI grouping
CC
Table 2-3
Notes
1
) must be
for
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